forked from OSchip/llvm-project
Make isScalarToVector to return false if the node is a scalar. This will prevent
DAGCombine from making an illegal transformation of bitcast of a scalar to a vector into a scalar_to_vector. llvm-svn: 119819
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@ -199,6 +199,8 @@ bool ISD::isScalarToVector(const SDNode *N) {
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if (N->getOperand(0).getOpcode() == ISD::UNDEF)
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if (N->getOperand(0).getOpcode() == ISD::UNDEF)
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return false;
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return false;
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unsigned NumElems = N->getNumOperands();
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unsigned NumElems = N->getNumOperands();
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if (NumElems == 1)
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return false;
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for (unsigned i = 1; i < NumElems; ++i) {
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for (unsigned i = 1; i < NumElems; ++i) {
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SDValue V = N->getOperand(i);
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SDValue V = N->getOperand(i);
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if (V.getOpcode() != ISD::UNDEF)
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if (V.getOpcode() != ISD::UNDEF)
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@ -0,0 +1,27 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
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define float @extractFloat1() nounwind {
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entry:
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; CHECK: 1065353216
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%tmp0 = bitcast <1 x double> <double 0x000000003F800000> to <2 x float>
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%tmp1 = extractelement <2 x float> %tmp0, i32 0
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ret float %tmp1
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}
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define float @extractFloat2() nounwind {
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entry:
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; CHECK: pxor %xmm0, %xmm0
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%tmp4 = bitcast <1 x double> <double 0x000000003F800000> to <2 x float>
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%tmp5 = extractelement <2 x float> %tmp4, i32 1
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ret float %tmp5
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}
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define i32 @extractInt2() nounwind {
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entry:
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; CHECK: xorl %eax, %eax
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%tmp4 = bitcast <1 x i64> <i64 256> to <2 x i32>
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%tmp5 = extractelement <2 x i32> %tmp4, i32 1
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ret i32 %tmp5
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}
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