forked from OSchip/llvm-project
[LV] Add new block to place recurrence splice, if needed.
In some cases, a recurrence splice instructions needs to be inserted between to regions, for example if the regions get re-arranged during sinking. Fixes #56146.
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@ -8944,7 +8944,11 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes(
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VPBasicBlock *InsertBlock = PrevRecipe->getParent();
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auto *Region = GetReplicateRegion(PrevRecipe);
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if (Region)
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InsertBlock = cast<VPBasicBlock>(Region->getSingleSuccessor());
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InsertBlock = dyn_cast<VPBasicBlock>(Region->getSingleSuccessor());
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if (!InsertBlock) {
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InsertBlock = new VPBasicBlock(Region->getName() + ".succ");
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VPBlockUtils::insertBlockAfter(InsertBlock, Region);
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}
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if (Region || PrevRecipe->isPhi())
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Builder.setInsertPoint(InsertBlock, InsertBlock->getFirstNonPhi());
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else
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@ -437,3 +437,85 @@ loop: ; preds = %loop, %entry
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exit: ; preds = %loop
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ret void
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}
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define void @need_new_block_after_sinking_pr56146(i32 %x, i32* %src) {
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; CHECK-LABEL: need_new_block_after_sinking_pr56146
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; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' {
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; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
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; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%.pn> = phi ir<0>, ir<%l>
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; CHECK-NEXT: EMIT vp<[[WIDE_IV:%.+]]> = WIDEN-CANONICAL-INDUCTION vp<[[CAN_IV]]>
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; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp ule vp<[[WIDE_IV]]> vp<[[BTC]]>
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; CHECK-NEXT: Successor(s): loop.0
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; CHECK-EMPTY:
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; CHECK-NEXT: loop.0:
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; CHECK-NEXT: Successor(s): pred.load
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.load: {
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; CHECK-NEXT: pred.load.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[CMP]]>
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; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.load.if:
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; CHECK-NEXT: REPLICATE ir<%l> = load ir<%src> (S->V)
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; CHECK-NEXT: Successor(s): pred.load.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.load.continue:
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; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[P_L:%.+]]> = ir<%l>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): pred.load.succ
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.load.succ:
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; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%.pn> ir<%l>
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; CHECK-NEXT: Successor(s): pred.sdiv
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.sdiv: {
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; CHECK-NEXT: pred.sdiv.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[CMP]]>
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; CHECK-NEXT: Successor(s): pred.sdiv.if, pred.sdiv.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.sdiv.if:
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; CHECK-NEXT: REPLICATE ir<%val> = sdiv vp<[[SPLICE]]>, ir<%x>
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; CHECK-NEXT: Successor(s): pred.sdiv.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.sdiv.continue:
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; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[P_VAL:%.+]]> = ir<%val>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): loop.1
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; CHECK-EMPTY:
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; CHECK-NEXT: loop.1:
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
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; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 2, %entry ], [ %iv.next, %loop ]
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%.pn = phi i32 [ 0, %entry ], [ %l, %loop ]
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%val = sdiv i32 %.pn, %x
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%l = load i32, i32* %src, align 4
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%iv.next = add nuw nsw i64 %iv, 1
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%ec = icmp ugt i64 %iv, 3
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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