forked from OSchip/llvm-project
[RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC
Previously we converted ISD condition codes to integers and stored them directly in our MIR instructions. The ISD enum kind of belongs to SelectionDAG so that seems like incorrect layering. This patch instead uses a CondCode node on RISCV::SELECT_CC until isel and then converts it from ISD encoding to a RISCV specific value. This value can be converted to/from the RISCV branch opcodes in the RISCV namespace. My larger motivation is to possibly support a microarchitectural feature of some CPUs where a short forward branch over a single instruction can be predicated internally. This will require a new pseudo instruction for select that needs to carry a branch condition and live probably until RISCVExpandPseudos. At that point it can be expanded to control flow without other instructions ending up in the predicated basic block. Using an ISD encoding in RISCVExpandPseudos doesn't seem like correct layering. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D107400
This commit is contained in:
Craig Topper
parent
20dfe051ab
commit
88bc29f5f2
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@ -83,6 +83,28 @@ public:
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void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
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void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
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// Return the RISC-V condition code that matches the given DAG integer
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// condition code. The CondCode must be one of those supported by the RISC-V
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// ISA (see translateSetCCForBranch).
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static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unsupported CondCode");
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case ISD::SETEQ:
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return RISCVCC::COND_EQ;
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case ISD::SETNE:
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return RISCVCC::COND_NE;
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case ISD::SETLT:
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return RISCVCC::COND_LT;
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case ISD::SETGE:
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return RISCVCC::COND_GE;
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case ISD::SETULT:
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return RISCVCC::COND_LTU;
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case ISD::SETUGE:
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return RISCVCC::COND_GEU;
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}
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}
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// Include the pieces autogenerated from the target description.
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#include "RISCVGenDAGISel.inc"
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@ -1071,28 +1071,6 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
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}
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}
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// Return the RISC-V branch opcode that matches the given DAG integer
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// condition code. The CondCode must be one of those supported by the RISC-V
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// ISA (see translateSetCCForBranch).
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static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unsupported CondCode");
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case ISD::SETEQ:
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return RISCV::BEQ;
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case ISD::SETNE:
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return RISCV::BNE;
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case ISD::SETLT:
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return RISCV::BLT;
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case ISD::SETGE:
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return RISCV::BGE;
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case ISD::SETULT:
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return RISCV::BLTU;
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case ISD::SETUGE:
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return RISCV::BGEU;
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}
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}
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RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) {
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assert(VT.isScalableVector() && "Expecting a scalable vector type");
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unsigned KnownSize = VT.getSizeInBits().getKnownMinValue();
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@ -3002,7 +2980,7 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
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SDValue TargetCC = DAG.getTargetConstant(CCVal, DL, XLenVT);
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SDValue TargetCC = DAG.getCondCode(CCVal);
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SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
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return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops);
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}
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@ -3011,7 +2989,7 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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// (select condv, truev, falsev)
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// -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
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SDValue Zero = DAG.getConstant(0, DL, XLenVT);
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SDValue SetNE = DAG.getTargetConstant(ISD::SETNE, DL, XLenVT);
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SDValue SetNE = DAG.getCondCode(ISD::SETNE);
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SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
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@ -6177,7 +6155,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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// Transform
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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auto CCVal = static_cast<ISD::CondCode>(N->getConstantOperandVal(2));
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ISD::CondCode CCVal = cast<CondCodeSDNode>(N->getOperand(2))->get();
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if (!ISD::isIntEqualitySetCC(CCVal))
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break;
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@ -6198,8 +6176,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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LHS = LHS.getOperand(0);
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translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
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SDValue TargetCC =
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DAG.getTargetConstant(CCVal, DL, Subtarget.getXLenVT());
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SDValue TargetCC = DAG.getCondCode(CCVal);
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return DAG.getNode(
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RISCVISD::SELECT_CC, DL, N->getValueType(0),
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{LHS, RHS, TargetCC, N->getOperand(3), N->getOperand(4)});
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@ -6219,8 +6196,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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if (isOneConstant(RHS) && DAG.MaskedValueIsZero(LHS, Mask)) {
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SDLoc DL(N);
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CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
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SDValue TargetCC =
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DAG.getTargetConstant(CCVal, DL, Subtarget.getXLenVT());
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SDValue TargetCC = DAG.getCondCode(CCVal);
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RHS = DAG.getConstant(0, DL, LHS.getValueType());
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return DAG.getNode(
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RISCVISD::SELECT_CC, DL, N->getValueType(0),
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@ -6881,7 +6857,8 @@ static bool isSelectPseudo(MachineInstr &MI) {
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}
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static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
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MachineBasicBlock *BB) {
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MachineBasicBlock *BB,
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const RISCVSubtarget &Subtarget) {
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// To "insert" Select_* instructions, we actually have to insert the triangle
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// control-flow pattern. The incoming instructions know the destination vreg
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// to set, the condition code register to branch on, the true/false values to
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@ -6908,7 +6885,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
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// related approach and more information.
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Register LHS = MI.getOperand(1).getReg();
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Register RHS = MI.getOperand(2).getReg();
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auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
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auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
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SmallVector<MachineInstr *, 4> SelectDebugValues;
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SmallSet<Register, 4> SelectDests;
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@ -6941,7 +6918,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
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}
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}
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const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
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const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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DebugLoc DL = MI.getDebugLoc();
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MachineFunction::iterator I = ++BB->getIterator();
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@ -6970,9 +6947,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
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HeadMBB->addSuccessor(TailMBB);
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// Insert appropriate branch.
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unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
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BuildMI(HeadMBB, DL, TII.get(Opcode))
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BuildMI(HeadMBB, DL, TII.getBrCond(CC))
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.addReg(LHS)
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.addReg(RHS)
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.addMBB(TailMBB);
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@ -7017,7 +6992,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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case RISCV::Select_FPR16_Using_CC_GPR:
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case RISCV::Select_FPR32_Using_CC_GPR:
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case RISCV::Select_FPR64_Using_CC_GPR:
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return emitSelectPseudo(MI, BB);
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return emitSelectPseudo(MI, BB, Subtarget);
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case RISCV::BuildPairF64Pseudo:
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return emitBuildPairF64Pseudo(MI, BB);
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case RISCV::SplitF64Pseudo:
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@ -469,6 +469,25 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
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}
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}
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static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
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switch (Opc) {
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default:
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return RISCVCC::COND_INVALID;
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case RISCV::BEQ:
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return RISCVCC::COND_EQ;
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case RISCV::BNE:
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return RISCVCC::COND_NE;
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case RISCV::BLT:
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return RISCVCC::COND_LT;
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case RISCV::BGE:
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return RISCVCC::COND_GE;
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case RISCV::BLTU:
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return RISCVCC::COND_LTU;
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case RISCV::BGEU:
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return RISCVCC::COND_GEU;
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}
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}
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// The contents of values added to Cond are not examined outside of
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// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
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// push BranchOpcode, Reg1, Reg2.
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@ -478,27 +497,47 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
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assert(LastInst.getDesc().isConditionalBranch() &&
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"Unknown conditional branch");
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Target = LastInst.getOperand(2).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
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unsigned CC = getCondFromBranchOpc(LastInst.getOpcode());
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Cond.push_back(MachineOperand::CreateImm(CC));
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Cond.push_back(LastInst.getOperand(0));
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Cond.push_back(LastInst.getOperand(1));
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}
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static unsigned getOppositeBranchOpcode(int Opc) {
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switch (Opc) {
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const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const {
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switch (CC) {
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default:
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llvm_unreachable("Unknown condition code!");
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case RISCVCC::COND_EQ:
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return get(RISCV::BEQ);
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case RISCVCC::COND_NE:
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return get(RISCV::BNE);
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case RISCVCC::COND_LT:
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return get(RISCV::BLT);
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case RISCVCC::COND_GE:
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return get(RISCV::BGE);
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case RISCVCC::COND_LTU:
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return get(RISCV::BLTU);
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case RISCVCC::COND_GEU:
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return get(RISCV::BGEU);
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}
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}
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RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unrecognized conditional branch");
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case RISCV::BEQ:
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return RISCV::BNE;
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case RISCV::BNE:
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return RISCV::BEQ;
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case RISCV::BLT:
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return RISCV::BGE;
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case RISCV::BGE:
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return RISCV::BLT;
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case RISCV::BLTU:
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return RISCV::BGEU;
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case RISCV::BGEU:
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return RISCV::BLTU;
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case RISCVCC::COND_EQ:
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return RISCVCC::COND_NE;
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case RISCVCC::COND_NE:
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return RISCVCC::COND_EQ;
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case RISCVCC::COND_LT:
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return RISCVCC::COND_GE;
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case RISCVCC::COND_GE:
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return RISCVCC::COND_LT;
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case RISCVCC::COND_LTU:
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return RISCVCC::COND_GEU;
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case RISCVCC::COND_GEU:
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return RISCVCC::COND_LTU;
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}
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}
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@ -624,9 +663,9 @@ unsigned RISCVInstrInfo::insertBranch(
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}
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// Either a one or two-way conditional branch.
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unsigned Opc = Cond[0].getImm();
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auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
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MachineInstr &CondMI =
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*BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
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*BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(CondMI);
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@ -680,7 +719,8 @@ unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
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bool RISCVInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert((Cond.size() == 3) && "Invalid branch condition!");
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Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
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auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
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Cond[0].setImm(getOppositeBranchCondition(CC));
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return false;
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}
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@ -24,12 +24,29 @@ namespace llvm {
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class RISCVSubtarget;
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namespace RISCVCC {
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enum CondCode {
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COND_EQ,
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COND_NE,
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COND_LT,
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COND_GE,
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COND_LTU,
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COND_GEU,
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COND_INVALID
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};
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CondCode getOppositeBranchCondition(CondCode);
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} // end of namespace RISCVCC
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class RISCVInstrInfo : public RISCVGenInstrInfo {
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public:
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explicit RISCVInstrInfo(RISCVSubtarget &STI);
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MCInst getNop() const override;
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const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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@ -23,6 +23,7 @@ def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
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// Target-dependent type requirements.
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def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
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def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
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SDTCisVT<3, OtherVT>,
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SDTCisSameAs<0, 4>,
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SDTCisSameAs<4, 5>]>;
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def SDT_RISCVBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
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@ -974,13 +975,27 @@ def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
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def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
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def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
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def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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RISCVCC::CondCode BrCC = getRISCVCCForIntCC(CC);
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return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
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}]>;
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def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
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node:$truev, node:$falsev),
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(riscv_selectcc node:$lhs, node:$rhs,
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node:$cc, node:$truev,
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node:$falsev), [{}],
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IntCCtoRISCVCC>;
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let usesCustomInserter = 1 in
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class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty>
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: Pseudo<(outs valty:$dst),
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(ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm,
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valty:$truev, valty:$falsev),
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[(set valty:$dst, (riscv_selectcc cmpty:$lhs, cmpty:$rhs,
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(XLenVT timm:$imm), valty:$truev, valty:$falsev))]>;
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[(set valty:$dst,
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(riscv_selectcc_frag:$imm cmpty:$lhs, cmpty:$rhs, cond,
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valty:$truev, valty:$falsev))]>;
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def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>;
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@ -140,9 +140,9 @@ body: |
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%0:gpr = COPY $x10
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%5:gpr = ANDI %0, 1
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%6:gpr = COPY $x0
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%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
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%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
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%8:gpr = ADDI %7, 1
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%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
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%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
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%10:gpr = ADD %7, killed %9
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$x10 = COPY %10
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PseudoRET implicit $x10
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@ -266,11 +266,11 @@ body: |
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%0:gpr = COPY $x10
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%5:gpr = ANDI %0, 1
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%6:gpr = COPY $x0
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%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
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%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
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DBG_VALUE %7, $noreg
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%8:gpr = ADDI %0, 1
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DBG_VALUE %8, $noreg
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%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
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%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
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DBG_VALUE %9, $noreg
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%10:gpr = ADD %7, killed %9
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$x10 = COPY %10
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