forked from OSchip/llvm-project
[X86] Add test cases for AVX1 broadcast fallback patterns when load can't be folded.
Also add test cases that do an insertelement to all elements for the 8 element vector tests. llvm-svn: 293602
This commit is contained in:
Craig Topper
parent
e9e84c8284
commit
88b0a47312
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@ -28,6 +28,40 @@ entry:
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ret <4 x i64> %vecinit6.i
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}
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define <4 x i64> @A2(i64* %ptr, i64* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: A2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl (%ecx), %edx
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; X32-NEXT: movl 4(%ecx), %ecx
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; X32-NEXT: movl %ecx, 4(%eax)
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; X32-NEXT: movl %edx, (%eax)
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; X32-NEXT: vmovd %edx, %xmm0
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; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; X32-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
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; X32-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: A2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: vmovq %rax, %xmm0
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; X64-NEXT: movq %rax, (%rsi)
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X64-NEXT: retq
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entry:
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%q = load i64, i64* %ptr, align 8
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store i64 %q, i64* %ptr2, align 8 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
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%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
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%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
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%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
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ret <4 x i64> %vecinit6.i
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}
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define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {
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; X32-LABEL: B:
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; X32: ## BB#0: ## %entry
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@ -48,6 +82,64 @@ entry:
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ret <8 x i32> %vecinit6.i
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}
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define <8 x i32> @B2(i32* %ptr) nounwind uwtable readnone ssp {
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; X32-LABEL: B2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vbroadcastss (%eax), %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: B2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: vbroadcastss (%rdi), %ymm0
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; X64-NEXT: retq
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entry:
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%q = load i32, i32* %ptr, align 4
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%vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
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%vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
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%vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
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%vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
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%vecinit8.i = insertelement <8 x i32> %vecinit6.i, i32 %q, i32 4
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%vecinit10.i = insertelement <8 x i32> %vecinit8.i, i32 %q, i32 5
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%vecinit12.i = insertelement <8 x i32> %vecinit10.i, i32 %q, i32 6
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%vecinit14.i = insertelement <8 x i32> %vecinit12.i, i32 %q, i32 7
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ret <8 x i32> %vecinit14.i
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}
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define <8 x i32> @B3(i32* %ptr, i32* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: B3:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl (%ecx), %ecx
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; X32-NEXT: vmovd %ecx, %xmm0
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; X32-NEXT: movl %ecx, (%eax)
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; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: B3:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: vmovd %eax, %xmm0
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; X64-NEXT: movl %eax, (%rsi)
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X64-NEXT: retq
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entry:
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%q = load i32, i32* %ptr, align 4
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store i32 %q, i32* %ptr2, align 4 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
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%vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
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%vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
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%vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
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%vecinit8.i = insertelement <8 x i32> %vecinit6.i, i32 %q, i32 4
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%vecinit10.i = insertelement <8 x i32> %vecinit8.i, i32 %q, i32 5
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%vecinit12.i = insertelement <8 x i32> %vecinit10.i, i32 %q, i32 6
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%vecinit14.i = insertelement <8 x i32> %vecinit12.i, i32 %q, i32 7
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ret <8 x i32> %vecinit14.i
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}
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define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {
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; X32-LABEL: C:
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; X32: ## BB#0: ## %entry
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@ -68,6 +160,34 @@ entry:
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ret <4 x double> %vecinit6.i
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}
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define <4 x double> @C2(double* %ptr, double* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: C2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X32-NEXT: vmovsd %xmm0, (%eax)
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; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: C2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: vmovsd %xmm0, (%rsi)
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X64-NEXT: retq
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entry:
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%q = load double, double* %ptr, align 8
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store double %q, double* %ptr2, align 8 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
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%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
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%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
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%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
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ret <4 x double> %vecinit6.i
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}
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define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {
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; X32-LABEL: D:
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; X32: ## BB#0: ## %entry
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@ -88,6 +208,62 @@ entry:
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ret <8 x float> %vecinit6.i
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}
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define <8 x float> @D2(float* %ptr) nounwind uwtable readnone ssp {
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; X32-LABEL: D2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vbroadcastss (%eax), %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: D2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: vbroadcastss (%rdi), %ymm0
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; X64-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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%vecinit.i = insertelement <8 x float> undef, float %q, i32 0
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%vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
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%vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
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%vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
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%vecinit8.i = insertelement <8 x float> %vecinit6.i, float %q, i32 4
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%vecinit10.i = insertelement <8 x float> %vecinit8.i, float %q, i32 5
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%vecinit12.i = insertelement <8 x float> %vecinit10.i, float %q, i32 6
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%vecinit14.i = insertelement <8 x float> %vecinit12.i, float %q, i32 7
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ret <8 x float> %vecinit14.i
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}
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define <8 x float> @D3(float* %ptr, float* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: D3:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: vmovd %xmm0, (%eax)
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; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: D3:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: vmovd %xmm0, (%rsi)
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; X64-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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store float %q, float* %ptr2, align 4 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <8 x float> undef, float %q, i32 0
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%vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
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%vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
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%vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
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%vecinit8.i = insertelement <8 x float> %vecinit6.i, float %q, i32 4
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%vecinit10.i = insertelement <8 x float> %vecinit8.i, float %q, i32 5
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%vecinit12.i = insertelement <8 x float> %vecinit10.i, float %q, i32 6
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%vecinit14.i = insertelement <8 x float> %vecinit12.i, float %q, i32 7
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ret <8 x float> %vecinit14.i
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}
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;;;; 128-bit versions
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define <4 x float> @e(float* %ptr) nounwind uwtable readnone ssp {
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@ -110,6 +286,32 @@ entry:
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ret <4 x float> %vecinit6.i
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}
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define <4 x float> @e2(float* %ptr, float* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: e2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: vmovd %xmm0, (%eax)
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; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: e2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: vmovd %xmm0, (%rsi)
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X64-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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store float %q, float* %ptr2, align 4 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
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%vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
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%vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
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%vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
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ret <4 x float> %vecinit6.i
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}
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; Don't broadcast constants on pre-AVX2 hardware.
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define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
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; X32-LABEL: _e2:
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@ -150,6 +352,34 @@ entry:
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ret <4 x i32> %vecinit6.i
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}
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define <4 x i32> @F2(i32* %ptr, i32* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: F2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl (%ecx), %ecx
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; X32-NEXT: movl %ecx, (%eax)
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; X32-NEXT: vmovd %ecx, %xmm0
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; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X32-NEXT: retl
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;
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; X64-LABEL: F2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: movl %eax, (%rsi)
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; X64-NEXT: vmovd %eax, %xmm0
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X64-NEXT: retq
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entry:
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%q = load i32, i32* %ptr, align 4
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store i32 %q, i32* %ptr2, align 4 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
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%vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %q, i32 1
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%vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %q, i32 2
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%vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %q, i32 3
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ret <4 x i32> %vecinit6.i
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}
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; FIXME: Pointer adjusted broadcasts
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define <4 x i32> @load_splat_4i32_4i32_1111(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
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@ -382,6 +612,36 @@ entry:
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ret <2 x i64> %vecinit2.i
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}
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define <2 x i64> @G2(i64* %ptr, i64* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: G2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl (%ecx), %edx
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; X32-NEXT: movl 4(%ecx), %ecx
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; X32-NEXT: movl %ecx, 4(%eax)
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; X32-NEXT: movl %edx, (%eax)
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; X32-NEXT: vmovd %edx, %xmm0
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; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; X32-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
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; X32-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: G2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: movq %rax, (%rsi)
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; X64-NEXT: vmovq %rax, %xmm0
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; X64-NEXT: retq
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entry:
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%q = load i64, i64* %ptr, align 8
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store i64 %q, i64* %ptr2, align 8 ; to create a chain to prevent broadcast
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%vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
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%vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1
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ret <2 x i64> %vecinit2.i
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}
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define <4 x i32> @H(<4 x i32> %a) {
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; X32-LABEL: H:
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; X32: ## BB#0: ## %entry
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@ -415,6 +675,30 @@ entry:
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ret <2 x double> %vecinit2.i
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}
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define <2 x double> @I2(double* %ptr, double* %ptr2) nounwind uwtable readnone ssp {
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; X32-LABEL: I2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X32-NEXT: vmovsd %xmm0, (%eax)
|
||||
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: I2:
|
||||
; X64: ## BB#0: ## %entry
|
||||
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
||||
; X64-NEXT: vmovsd %xmm0, (%rsi)
|
||||
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%q = load double, double* %ptr, align 4
|
||||
store double %q, double* %ptr2, align 4 ; to create a chain to prevent broadcast
|
||||
%vecinit.i = insertelement <2 x double> undef, double %q, i32 0
|
||||
%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
|
||||
ret <2 x double> %vecinit2.i
|
||||
}
|
||||
|
||||
define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
|
||||
; X32-LABEL: _RR:
|
||||
; X32: ## BB#0: ## %entry
|
||||
|
|
|
|||
Loading…
Reference in New Issue