forked from OSchip/llvm-project
[COFF, ARM64] Implement Intrinsic.sponentry for AArch64
Summary: This patch adds Intrinsic.sponentry. This intrinsic is required to correctly support setjmp for AArch64 Windows platform. Reviewers: mgrang, TomTan, rnk, compnerd, mstorsjo, efriedma Reviewed By: efriedma Subscribers: majnemer, chrib, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D53673 llvm-svn: 345791
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@ -10330,6 +10330,27 @@ of the obvious source-language caller.
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This intrinsic is only implemented for x86.
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'``llvm.sponentry``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i8* @llvm.sponentry()
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Overview:
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"""""""""
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The '``llvm.sponentry``' intrinsic returns the stack pointer value at
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the entry of the current function calling this intrinsic.
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Semantics:
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""""""""""
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Note this intrinsic is only verified on AArch64.
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'``llvm.frameaddress``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -70,7 +70,7 @@ namespace ISD {
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/// of the frame or return address to return. An index of zero corresponds
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/// to the current function's frame or return address, an index of one to
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/// the parent's frame or return address, and so on.
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FRAMEADDR, RETURNADDR, ADDROFRETURNADDR,
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FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY,
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/// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
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/// Materializes the offset from the local object pointer of another
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@ -320,6 +320,7 @@ def int_gcwrite : Intrinsic<[],
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def int_returnaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_addressofreturnaddress : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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def int_frameaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_sponentry : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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def int_read_register : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],
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[IntrReadMem], "llvm.read_register">;
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def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty],
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@ -1059,6 +1059,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
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case ISD::FRAMEADDR:
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case ISD::RETURNADDR:
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case ISD::ADDROFRETURNADDR:
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case ISD::SPONENTRY:
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// These operations lie about being legal: when they claim to be legal,
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// they should actually be custom-lowered.
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Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
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@ -5050,6 +5050,10 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
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TLI.getPointerTy(DAG.getDataLayout())));
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return nullptr;
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case Intrinsic::sponentry:
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setValue(&I, DAG.getNode(ISD::SPONENTRY, sdl,
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TLI.getPointerTy(DAG.getDataLayout())));
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return nullptr;
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case Intrinsic::frameaddress:
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setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
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TLI.getPointerTy(DAG.getDataLayout()),
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@ -124,6 +124,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::RETURNADDR: return "RETURNADDR";
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case ISD::ADDROFRETURNADDR: return "ADDROFRETURNADDR";
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case ISD::FRAMEADDR: return "FRAMEADDR";
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case ISD::SPONENTRY: return "SPONENTRY";
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case ISD::LOCAL_RECOVER: return "LOCAL_RECOVER";
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case ISD::READ_REGISTER: return "READ_REGISTER";
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case ISD::WRITE_REGISTER: return "WRITE_REGISTER";
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@ -3450,6 +3450,22 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
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updateValueMap(II, SrcReg);
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return true;
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}
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case Intrinsic::sponentry: {
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MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
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// SP = FP + Fixed Object + 16
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MVT VT = TLI.getPointerTy(DL);
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int FI = MFI.CreateFixedObject(4, 0, false);
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::ADDXri), ResultReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addImm(0);
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updateValueMap(II, ResultReg);
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return true;
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}
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case Intrinsic::memcpy:
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case Intrinsic::memmove: {
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const auto *MTI = cast<MemTransferInst>(II);
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@ -2863,6 +2863,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
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return LowerFP_EXTEND(Op, DAG);
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case ISD::FRAMEADDR:
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return LowerFRAMEADDR(Op, DAG);
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case ISD::SPONENTRY:
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return LowerSPONENTRY(Op, DAG);
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case ISD::RETURNADDR:
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return LowerRETURNADDR(Op, DAG);
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case ISD::INSERT_VECTOR_ELT:
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@ -5171,6 +5173,16 @@ SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
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return FrameAddr;
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}
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SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
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SelectionDAG &DAG) const {
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MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
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EVT VT = getPointerTy(DAG.getDataLayout());
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SDLoc DL(Op);
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int FI = MFI.CreateFixedObject(4, 0, false);
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return DAG.getFrameIndex(FI, VT);
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}
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// FIXME? Maybe this could be a TableGen attribute on some registers and
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// this table could be generated automatically from RegInfo.
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unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
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@ -617,6 +617,7 @@ private:
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SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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@ -0,0 +1,104 @@
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; RUN: llc -mtriple=aarch64-windows-msvc -disable-fp-elim %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64-windows-msvc -fast-isel -disable-fp-elim %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s --check-prefix=NOFP
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; RUN: llc -mtriple=aarch64-windows-msvc -fast-isel %s -o - | FileCheck %s --check-prefix=NOFP
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@env2 = common dso_local global [24 x i64]* null, align 8
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define dso_local void @bar() {
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%1 = call i8* @llvm.sponentry()
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%2 = load [24 x i64]*, [24 x i64]** @env2, align 8
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%3 = getelementptr inbounds [24 x i64], [24 x i64]* %2, i32 0, i32 0
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%4 = bitcast i64* %3 to i8*
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%5 = call i32 @_setjmpex(i8* %4, i8* %1) #2
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ret void
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}
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; CHECK: bar:
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; CHECK: mov x29, sp
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; CHECK: add x1, x29, #16
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; CEHCK: bl _setjmpex
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; NOFP: str x30, [sp, #-16]!
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; NOFP: add x1, sp, #16
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define dso_local void @foo([24 x i64]*) {
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%2 = alloca [24 x i64]*, align 8
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%3 = alloca i32, align 4
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%4 = alloca [100 x i32], align 4
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store [24 x i64]* %0, [24 x i64]** %2, align 8
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%5 = call i8* @llvm.sponentry()
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%6 = load [24 x i64]*, [24 x i64]** %2, align 8
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%7 = getelementptr inbounds [24 x i64], [24 x i64]* %6, i32 0, i32 0
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%8 = bitcast i64* %7 to i8*
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%9 = call i32 @_setjmpex(i8* %8, i8* %5)
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store i32 %9, i32* %3, align 4
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ret void
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}
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; CHECK: foo:
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; CHECK: sub sp, sp, #448
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; CHECK: add x29, sp, #432
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; CHECK: add x1, x29, #16
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; CEHCK: bl _setjmpex
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; NOFP: sub sp, sp, #432
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; NOFP: add x1, sp, #432
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define dso_local void @var_args(i8*, ...) {
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%2 = alloca i8*, align 8
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%3 = alloca i8*, align 8
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store i8* %0, i8** %2, align 8
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%4 = bitcast i8** %3 to i8*
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call void @llvm.va_start(i8* %4)
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%5 = load i8*, i8** %3, align 8
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%6 = getelementptr inbounds i8, i8* %5, i64 8
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store i8* %6, i8** %3, align 8
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%7 = bitcast i8* %5 to i32*
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%8 = load i32, i32* %7, align 8
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%9 = bitcast i8** %3 to i8*
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call void @llvm.va_end(i8* %9)
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%10 = call i8* @llvm.sponentry()
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%11 = load [24 x i64]*, [24 x i64]** @env2, align 8
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%12 = getelementptr inbounds [24 x i64], [24 x i64]* %11, i32 0, i32 0
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%13 = bitcast i64* %12 to i8*
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%14 = call i32 @_setjmpex(i8* %13, i8* %10) #3
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ret void
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}
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; CHECK: var_args:
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; CHECK: sub sp, sp, #96
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; CHECK: add x29, sp, #16
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; CHECK: add x1, x29, #80
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; CEHCK: bl _setjmpex
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; NOFP: sub sp, sp, #96
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; NOFP: add x1, sp, #96
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define dso_local void @manyargs(i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, i64 %x8, i64 %x9, i64 %x10) {
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%1 = call i8* @llvm.sponentry()
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%2 = load [24 x i64]*, [24 x i64]** @env2, align 8
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%3 = getelementptr inbounds [24 x i64], [24 x i64]* %2, i32 0, i32 0
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%4 = bitcast i64* %3 to i8*
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%5 = call i32 @_setjmpex(i8* %4, i8* %1) #2
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ret void
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}
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; CHECK: manyargs:
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; CHECK: stp x29, x30, [sp, #-16]!
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; CHECK: add x1, x29, #16
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; NOFP: str x30, [sp, #-16]!
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; NOFP: add x1, sp, #16
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; Function Attrs: nounwind readnone
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declare i8* @llvm.sponentry()
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; Function Attrs: returns_twice
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declare dso_local i32 @_setjmpex(i8*, i8*)
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; Function Attrs: nounwind
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declare void @llvm.va_start(i8*) #1
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; Function Attrs: nounwind
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declare void @llvm.va_end(i8*) #1
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