forked from OSchip/llvm-project
[WebAssembly] Fix handling of COPY instructions in WebAssemblyRegStackify.
Move RegStackify after coalescing and teach it to use LiveIntervals instead of depending on SSA form. This avoids a problem where a register in a COPY instruction is stackified and then subsequently coalesced with a register that is not stackified. This also puts it after the scheduler, which allows us to simplify the EXPR_STACK constraint, as we no longer have instructions being reordered after stackification and before coloring. llvm-svn: 256402
This commit is contained in:
Dan Gohman
parent
99d235329f
commit
8887d1faed
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@ -320,11 +320,12 @@ static void PlaceBlockMarker(MachineBasicBlock &MBB, MachineFunction &MF,
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// the BLOCK needs to be above the LOOP.
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InsertPos = Header->begin();
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} else {
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// Otherwise, insert the BLOCK as late in Header as we can, but before any
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// existing BLOCKs.
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// Otherwise, insert the BLOCK as late in Header as we can, but before the
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// beginning of the local expression tree and any nested BLOCKs.
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InsertPos = Header->getFirstTerminator();
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while (InsertPos != Header->begin() &&
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prev(InsertPos)->getOpcode() == WebAssembly::BLOCK)
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prev(InsertPos)->definesRegister(WebAssembly::EXPR_STACK) &&
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prev(InsertPos)->getOpcode() != WebAssembly::LOOP)
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--InsertPos;
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}
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@ -50,9 +50,13 @@ def TABLESWITCH_I64 : I<(outs), (ins I64:$index, bb_op:$default, variable_ops),
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"tableswitch\t$index, $default">;
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} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
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// Placemarkers to indicate the start of a block or loop scope.
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// Placemarkers to indicate the start of a block or loop scope. These
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// use/clobber EXPR_STACK to prevent them from being moved into the middle of
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// an expression tree.
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let Uses = [EXPR_STACK], Defs = [EXPR_STACK] in {
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def BLOCK : I<(outs), (ins bb_op:$dst), [], "block \t$dst">;
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def LOOP : I<(outs), (ins bb_op:$dst), [], "loop \t$dst">;
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} // Uses = [EXPR_STACK], Defs = [EXPR_STACK]
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// No-op to indicate to the AsmPrinter that a loop ends here, so a
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// basic block label is needed even if it wouldn't otherwise appear so.
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@ -24,6 +24,7 @@
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" // for WebAssembly::ARGUMENT_*
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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@ -42,8 +43,12 @@ class WebAssemblyRegStackify final : public MachineFunctionPass {
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<AAResultsWrapperPass>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(LiveVariablesID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -61,59 +66,68 @@ FunctionPass *llvm::createWebAssemblyRegStackify() {
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}
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// Decorate the given instruction with implicit operands that enforce the
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// expression stack ordering constraints needed for an instruction which is
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// consumed by an instruction using the expression stack.
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static void ImposeStackInputOrdering(MachineInstr *MI) {
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// expression stack ordering constraints for an instruction which is on
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// the expression stack.
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static void ImposeStackOrdering(MachineInstr *MI) {
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// Write the opaque EXPR_STACK register.
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if (!MI->definesRegister(WebAssembly::EXPR_STACK))
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MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
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/*isDef=*/true,
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/*isImp=*/true));
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}
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// Decorate the given instruction with implicit operands that enforce the
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// expression stack ordering constraints for an instruction which is on
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// the expression stack.
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static void ImposeStackOrdering(MachineInstr *MI, MachineRegisterInfo &MRI) {
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ImposeStackInputOrdering(MI);
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// Also read the opaque EXPR_STACK register.
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if (!MI->readsRegister(WebAssembly::EXPR_STACK))
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MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
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/*isDef=*/false,
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/*isImp=*/true));
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// Also, mark any inputs to this instruction as being consumed by an
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// instruction on the expression stack.
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// TODO: Find a lighter way to describe the appropriate constraints.
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for (MachineOperand &MO : MI->uses()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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MachineInstr *Def = MRI.getVRegDef(Reg);
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if (Def->getOpcode() == TargetOpcode::PHI)
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continue;
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ImposeStackInputOrdering(Def);
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}
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}
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// Test whether it's safe to move Def to just before Insert. Note that this
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// doesn't account for physical register dependencies, because WebAssembly
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// doesn't have any (other than special ones like EXPR_STACK).
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// Test whether it's safe to move Def to just before Insert.
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// TODO: Compute memory dependencies in a way that doesn't require always
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// walking the block.
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// TODO: Compute memory dependencies in a way that uses AliasAnalysis to be
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// more precise.
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static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert,
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AliasAnalysis &AA) {
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AliasAnalysis &AA, LiveIntervals &LIS,
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MachineRegisterInfo &MRI) {
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assert(Def->getParent() == Insert->getParent());
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bool SawStore = false, SawSideEffects = false;
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MachineBasicBlock::const_iterator D(Def), I(Insert);
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// Check for register dependencies.
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for (const MachineOperand &MO : Def->operands()) {
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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// If the register is dead here and at Insert, ignore it.
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if (MO.isDead() && Insert->definesRegister(Reg) &&
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!Insert->readsRegister(Reg))
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// If the physical register is never modified, ignore it.
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if (!MRI.isPhysRegModified(Reg))
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continue;
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// Otherwise, it's a physical register with unknown liveness.
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return false;
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}
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// Ask LiveIntervals whether moving this virtual register use or def to
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// Insert will change value numbers are seen.
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const LiveInterval &LI = LIS.getInterval(Reg);
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VNInfo *DefVNI = MO.isDef() ?
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LI.getVNInfoAt(LIS.getInstructionIndex(Def).getRegSlot()) :
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LI.getVNInfoBefore(LIS.getInstructionIndex(Def));
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assert(DefVNI && "Instruction input missing value number");
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VNInfo *InsVNI = LI.getVNInfoBefore(LIS.getInstructionIndex(Insert));
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if (InsVNI && DefVNI != InsVNI)
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return false;
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}
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// Check for memory dependencies and side effects.
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for (--I; I != D; --I)
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SawSideEffects |= I->isSafeToMove(&AA, SawStore);
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return !(SawStore && Def->mayLoad() && !Def->isInvariantLoad(&AA)) &&
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!(SawSideEffects && !Def->isSafeToMove(&AA, SawStore));
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}
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@ -127,8 +141,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
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AliasAnalysis &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
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assert(MRI.isSSA() && "RegStackify depends on SSA form");
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LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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// Walk the instructions from the bottom up. Currently we don't look past
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// block boundaries, and the blocks aren't ordered so the block visitation
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@ -154,19 +167,10 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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continue;
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unsigned Reg = Op.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// An instruction with a physical register. Conservatively mark it as
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// an expression stack input so that it isn't reordered with anything
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// in an expression stack which might use it (physical registers
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// aren't in SSA form so it's not trivial to determine this).
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// TODO: Be less conservative.
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ImposeStackInputOrdering(Insert);
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continue;
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}
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// Only consider registers with a single definition.
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// TODO: Eventually we may relax this, to stackify phi transfers.
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MachineInstr *Def = MRI.getVRegDef(Reg);
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MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
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if (!Def)
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continue;
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@ -198,26 +202,26 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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continue;
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// For now, be conservative and don't look across block boundaries.
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// TODO: Be more aggressive.
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// TODO: Be more aggressive?
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if (Def->getParent() != &MBB)
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continue;
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// Don't move instructions that have side effects or memory dependencies
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// or other complications.
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if (!IsSafeToMove(Def, Insert, AA))
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if (!IsSafeToMove(Def, Insert, AA, LIS, MRI))
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continue;
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Changed = true;
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AnyStackified = true;
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// Move the def down and nest it in the current instruction.
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MBB.insert(MachineBasicBlock::instr_iterator(Insert),
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Def->removeFromParent());
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MBB.splice(Insert, &MBB, Def);
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LIS.handleMove(Def);
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MFI.stackifyVReg(Reg);
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ImposeStackOrdering(Def, MRI);
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ImposeStackOrdering(Def);
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Insert = Def;
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}
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if (AnyStackified)
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ImposeStackOrdering(&MI, MRI);
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ImposeStackOrdering(&MI);
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}
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}
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@ -165,12 +165,6 @@ void WebAssemblyPassConfig::addPreRegAlloc() {
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// Prepare store instructions for register stackifying.
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addPass(createWebAssemblyStoreResults());
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// Mark registers as representing wasm's expression stack.
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addPass(createWebAssemblyRegStackify());
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// The register coalescing pass has a bad interaction with COPY MIs which have
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// EXPR_STACK as an extra operand
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// disablePass(&RegisterCoalescerID);
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}
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void WebAssemblyPassConfig::addPostRegAlloc() {
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@ -184,6 +178,9 @@ void WebAssemblyPassConfig::addPostRegAlloc() {
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// Fails with: should be run after register allocation.
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disablePass(&MachineCopyPropagationID);
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// Mark registers as representing wasm's expression stack.
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addPass(createWebAssemblyRegStackify());
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// Run the register coloring pass to reduce the total number of registers.
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addPass(createWebAssemblyRegColoring());
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@ -464,7 +464,7 @@ if.end:
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; CHECK: block BB13_8{{$}}
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; CHECK-NEXT: block BB13_7{{$}}
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; CHECK-NEXT: block BB13_4{{$}}
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; CHECK-NEXT: br_if $pop{{[0-9]*}}, BB13_4{{$}}
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; CHECK: br_if $pop{{[0-9]*}}, BB13_4{{$}}
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; CHECK-NEXT: block BB13_3{{$}}
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; CHECK: br_if $pop{{[0-9]*}}, BB13_3{{$}}
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; CHECK: br_if $pop{{[0-9]*}}, BB13_7{{$}}
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@ -483,7 +483,7 @@ if.end:
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; OPT: block BB13_8{{$}}
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; OPT-NEXT: block BB13_7{{$}}
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; OPT-NEXT: block BB13_4{{$}}
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; OPT-NEXT: br_if $pop{{[0-9]*}}, BB13_4{{$}}
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; OPT: br_if $pop{{[0-9]*}}, BB13_4{{$}}
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; OPT-NEXT: block BB13_3{{$}}
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; OPT: br_if $pop{{[0-9]*}}, BB13_3{{$}}
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; OPT: br_if $pop{{[0-9]*}}, BB13_7{{$}}
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@ -642,7 +642,7 @@ second:
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; CHECK-NEXT: loop BB16_5{{$}}
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; CHECK-NOT: block
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; CHECK: block BB16_4{{$}}
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; CHECK-NEXT: br_if {{[^,]*}}, BB16_4{{$}}
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; CHECK: br_if {{[^,]*}}, BB16_4{{$}}
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; CHECK-NOT: block
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; CHECK: br_if {{[^,]*}}, BB16_1{{$}}
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; CHECK-NOT: block
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@ -907,7 +907,7 @@ bb6:
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; CHECK-NEXT: br_if {{[^,]*}}, BB20_4{{$}}
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; CHECK-NOT: block
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; CHECK: block BB20_3{{$}}
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; CHECK-NEXT: br_if {{[^,]*}}, BB20_3{{$}}
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; CHECK: br_if {{[^,]*}}, BB20_3{{$}}
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; CHECK-NOT: block
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; CHECK: br_if {{[^,]*}}, BB20_6{{$}}
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; CHECK-NEXT: BB20_3:
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@ -933,7 +933,7 @@ bb6:
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; OPT-NEXT: br_if $0, BB20_4{{$}}
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; OPT-NOT: block
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; OPT: block BB20_3{{$}}
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; OPT-NEXT: br_if $0, BB20_3{{$}}
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; OPT: br_if $0, BB20_3{{$}}
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; OPT-NOT: block
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; OPT: br_if $0, BB20_8{{$}}
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; OPT-NEXT: BB20_3:
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@ -991,7 +991,7 @@ bb8:
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; CHECK: block BB21_7{{$}}
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; CHECK-NEXT: block BB21_6{{$}}
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; CHECK-NEXT: block BB21_4{{$}}
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; CHECK-NEXT: br_if {{[^,]*}}, BB21_4{{$}}
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; CHECK: br_if {{[^,]*}}, BB21_4{{$}}
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; CHECK-NOT: block
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; CHECK: br_if {{[^,]*}}, BB21_7{{$}}
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; CHECK-NOT: block
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@ -1015,7 +1015,7 @@ bb8:
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; OPT: block BB21_7{{$}}
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; OPT-NEXT: block BB21_6{{$}}
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; OPT-NEXT: block BB21_4{{$}}
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; OPT-NEXT: br_if {{[^,]*}}, BB21_4{{$}}
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; OPT: br_if {{[^,]*}}, BB21_4{{$}}
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; OPT-NOT: block
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; OPT: br_if {{[^,]*}}, BB21_7{{$}}
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; OPT-NOT: block
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@ -53,8 +53,9 @@ define i32 @yes1(i32* %q) {
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; CHECK-NEXT: .param i32, i32, i32, i32{{$}}
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; CHECK-NEXT: .result i32{{$}}
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; CHECK-NEXT: .local i32, i32{{$}}
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; CHECK-NEXT: i32.const $4=, 1{{$}}
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; CHECK-NEXT: i32.const $5=, 2{{$}}
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; CHECK-NEXT: i32.const $4=, 1{{$}}
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; CHECK-NEXT: block BB4_2{{$}}
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; CHECK-NEXT: i32.lt_s $push0=, $0, $4{{$}}
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; CHECK-NEXT: i32.lt_s $push1=, $1, $5{{$}}
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; CHECK-NEXT: i32.xor $push4=, $pop0, $pop1{{$}}
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@ -63,7 +64,6 @@ define i32 @yes1(i32* %q) {
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; CHECK-NEXT: i32.xor $push5=, $pop2, $pop3{{$}}
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; CHECK-NEXT: i32.xor $push6=, $pop4, $pop5{{$}}
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; CHECK-NEXT: i32.ne $push7=, $pop6, $4{{$}}
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; CHECK-NEXT: block BB4_2{{$}}
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; CHECK-NEXT: br_if $pop7, BB4_2{{$}}
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; CHECK-NEXT: i32.const $push8=, 0{{$}}
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; CHECK-NEXT: return $pop8{{$}}
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@ -85,4 +85,42 @@ false:
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ret i32 1
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}
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; Test an interesting case where the load has multiple uses and cannot
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; be trivially stackified.
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; CHECK-LABEL: multiple_uses:
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; CHECK-NEXT: .param i32, i32, i32{{$}}
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; CHECK-NEXT: .local i32{{$}}
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; CHECK-NEXT: i32.load $3=, 0($2){{$}}
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; CHECK-NEXT: block BB5_3{{$}}
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; CHECK-NEXT: i32.ge_u $push0=, $3, $1{{$}}
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; CHECK-NEXT: br_if $pop0, BB5_3{{$}}
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; CHECK-NEXT: i32.lt_u $push1=, $3, $0{{$}}
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; CHECK-NEXT: br_if $pop1, BB5_3{{$}}
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; CHECK-NEXT: i32.store $discard=, 0($2), $3{{$}}
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; CHECK-NEXT: BB5_3:
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; CHECK-NEXT: return{{$}}
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define void @multiple_uses(i32* %arg0, i32* %arg1, i32* %arg2) nounwind {
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bb:
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br label %loop
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loop:
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%tmp7 = load i32, i32* %arg2
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%tmp8 = inttoptr i32 %tmp7 to i32*
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%tmp9 = icmp uge i32* %tmp8, %arg1
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%tmp10 = icmp ult i32* %tmp8, %arg0
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%tmp11 = or i1 %tmp9, %tmp10
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br i1 %tmp11, label %back, label %then
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then:
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store i32 %tmp7, i32* %arg2
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br label %back
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back:
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br i1 undef, label %return, label %loop
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return:
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ret void
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}
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!0 = !{}
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