From 8858fa8552dcc5d268f14c1b64714121612d73c0 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Fri, 5 Oct 2018 17:36:51 +0000
Subject: [PATCH] [x86] add test for (X - 0.0) vector with undef elts; NFC

llvm-svn: 343863
---
 llvm/test/CodeGen/X86/vec_fneg.ll | 32 ++++++++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/X86/vec_fneg.ll b/llvm/test/CodeGen/X86/vec_fneg.ll
index 26c233f7db22..e9dc88ea4338 100644
--- a/llvm/test/CodeGen/X86/vec_fneg.ll
+++ b/llvm/test/CodeGen/X86/vec_fneg.ll
@@ -99,15 +99,15 @@ define <2 x float> @fneg_bitcast(i64 %i) nounwind {
   ret <2 x float> %fneg
 }
 
-define <4 x float> @undef_elts_v4f32(<4 x float> %x) {
-; X32-SSE-LABEL: undef_elts_v4f32:
+define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) {
+; X32-SSE-LABEL: fneg_undef_elts_v4f32:
 ; X32-SSE:       # %bb.0:
 ; X32-SSE-NEXT:    movaps {{.*#+}} xmm1 = <-0,u,u,-0>
 ; X32-SSE-NEXT:    subps %xmm0, %xmm1
 ; X32-SSE-NEXT:    movaps %xmm1, %xmm0
 ; X32-SSE-NEXT:    retl
 ;
-; X64-SSE-LABEL: undef_elts_v4f32:
+; X64-SSE-LABEL: fneg_undef_elts_v4f32:
 ; X64-SSE:       # %bb.0:
 ; X64-SSE-NEXT:    movaps {{.*#+}} xmm1 = <-0,u,u,-0>
 ; X64-SSE-NEXT:    subps %xmm0, %xmm1
@@ -117,3 +117,29 @@ define <4 x float> @undef_elts_v4f32(<4 x float> %x) {
   ret <4 x float> %r
 }
 
+; This isn't fneg, but similarly check that (X - 0.0) is simplified.
+
+define <4 x float> @fsub0_undef_elts_v4f32(<4 x float> %x) {
+; X32-SSE1-LABEL: fsub0_undef_elts_v4f32:
+; X32-SSE1:       # %bb.0:
+; X32-SSE1-NEXT:    retl
+;
+; X32-SSE2-LABEL: fsub0_undef_elts_v4f32:
+; X32-SSE2:       # %bb.0:
+; X32-SSE2-NEXT:    xorps %xmm1, %xmm1
+; X32-SSE2-NEXT:    subps %xmm1, %xmm0
+; X32-SSE2-NEXT:    retl
+;
+; X64-SSE1-LABEL: fsub0_undef_elts_v4f32:
+; X64-SSE1:       # %bb.0:
+; X64-SSE1-NEXT:    retq
+;
+; X64-SSE2-LABEL: fsub0_undef_elts_v4f32:
+; X64-SSE2:       # %bb.0:
+; X64-SSE2-NEXT:    xorps %xmm1, %xmm1
+; X64-SSE2-NEXT:    subps %xmm1, %xmm0
+; X64-SSE2-NEXT:    retq
+  %r = fsub <4 x float> %x, <float 0.0, float undef, float 0.0, float undef>
+  ret <4 x float> %r
+}
+