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[X86][SSE] LowerScalarImmediateShift - ensure shift amount correctness. NFCI. 

Assert that the shift amount is in range and create vXi8 shift masks in a way that doesn't cause MSVC/cppcheck shift result is truncated then extended warnings.

llvm-svn: 365024
This commit is contained in:
Simon Pilgrim 2019-07-03 10:47:33 +00:00
parent 3e41b97f14
commit 8853bd9592
1 changed files with 4 additions and 2 deletions
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6
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -25016,6 +25016,8 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
APInt APIntShiftAmt;
if (!isConstantSplat(Amt, APIntShiftAmt))
return SDValue();
assert(APIntShiftAmt.ult(VT.getScalarSizeInBits()) &&
"Out of range shift amount");
uint64_t ShiftAmt = APIntShiftAmt.getZExtValue();
if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
@ -25057,8 +25059,8 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
ShiftAmt, DAG);
SHL = DAG.getBitcast(VT, SHL);
// Zero out the rightmost bits.
return DAG.getNode(ISD::AND, dl, VT, SHL,
DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, VT));
APInt Mask = APInt::getHighBitsSet(8, 8 - ShiftAmt);
return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT));
}
if (Op.getOpcode() == ISD::SRL) {
// Make a large shift.