forked from OSchip/llvm-project
[RISCV] Use defvar to simplify some code. NFC
Rather than wrapping a def around a list, we can just make a defvar of the list.
This commit is contained in:
Craig Topper
parent
41454ab256
commit
8811a87e8c
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@ -71,25 +71,19 @@ def V_MF4 : LMULInfo<0b110, 2, VR, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR, "M
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def V_MF2 : LMULInfo<0b111, 4, VR, VR, VR, VR,/*NoVReg*/VR, "MF2">;
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// Used to iterate over all possible LMULs.
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def MxList {
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list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
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}
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defvar MxList = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
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// Used for widening and narrowing instructions as it doesn't contain M8.
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def MxListW {
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list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4];
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}
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defvar MxListW = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4];
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// Use for zext/sext.vf2
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def MxListVF2 {
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list<LMULInfo> m = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
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}
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defvar MxListVF2 = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
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// Use for zext/sext.vf4
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def MxListVF4 {
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list<LMULInfo> m = [V_MF2, V_M1, V_M2, V_M4, V_M8];
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}
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defvar MxListVF4 = [V_MF2, V_M1, V_M2, V_M4, V_M8];
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// Use for zext/sext.vf8
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def MxListVF8 {
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list<LMULInfo> m = [V_M1, V_M2, V_M4, V_M8];
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}
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defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8];
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class FPR_Info<RegisterClass regclass, string fx> {
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RegisterClass fprclass = regclass;
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@ -100,13 +94,10 @@ def SCALAR_F16 : FPR_Info<FPR16, "F16">;
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def SCALAR_F32 : FPR_Info<FPR32, "F32">;
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def SCALAR_F64 : FPR_Info<FPR64, "F64">;
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def FPList {
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list<FPR_Info> fpinfo = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
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}
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defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
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// Used for widening instructions. It excludes F64.
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def FPListW {
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list<FPR_Info> fpinfo = [SCALAR_F16, SCALAR_F32];
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}
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defvar FPListW = [SCALAR_F16, SCALAR_F32];
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class MxSet<int eew> {
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list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
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@ -1504,7 +1495,7 @@ multiclass VPseudoVSFS_M {
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}
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multiclass VPseudoVID_V {
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in {
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def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
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Sched<[WriteVMIdxV, ReadVMask]>;
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@ -1524,7 +1515,7 @@ multiclass VPseudoNullaryPseudoM <string BaseInst> {
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multiclass VPseudoVIOT_M {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in {
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def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
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Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
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@ -1535,7 +1526,7 @@ multiclass VPseudoVIOT_M {
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}
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multiclass VPseudoVCPR_V {
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in
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def _VM # "_" # m.MX : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
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Sched<[WriteVCompressV, ReadVCompressV, ReadVCompressV]>;
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@ -1596,12 +1587,12 @@ multiclass VPseudoTiedBinary<VReg RetClass,
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}
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multiclass VPseudoBinaryV_VV<string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
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}
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multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
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foreach m = MxList.m in {
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foreach m = MxList in {
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foreach sew = EEWList in {
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defvar octuple_lmul = m.octuple;
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// emul = lmul * eew / sew
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@ -1617,38 +1608,38 @@ multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
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}
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multiclass VPseudoBinaryV_VX<string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
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}
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multiclass VPseudoVSLD1_VX<string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
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Sched<[WriteVISlide1X, ReadVISlideV, ReadVISlideX, ReadVMask]>;
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}
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multiclass VPseudoBinaryV_VF<string Constraint = ""> {
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foreach m = MxList.m in
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foreach f = FPList.fpinfo in
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foreach m = MxList in
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foreach f = FPList in
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defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,
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f.fprclass, m, Constraint>;
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}
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multiclass VPseudoVSLD1_VF<string Constraint = ""> {
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foreach m = MxList.m in
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foreach f = FPList.fpinfo in
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foreach m = MxList in
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foreach f = FPList in
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defm "_V" # f.FX :
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VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
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Sched<[WriteVFSlide1F, ReadVFSlideV, ReadVFSlideF, ReadVMask]>;
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}
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multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
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}
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multiclass VPseudoVALU_MM {
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foreach m = MxList.m in
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foreach m = MxList in
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let VLMul = m.value in {
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def "_MM_" # m.MX : VPseudoBinaryNoMask<VR, VR, VR, "">,
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Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>;
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@ -1663,27 +1654,27 @@ multiclass VPseudoVALU_MM {
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// at least 1, and the overlap is in the highest-numbered part of the
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// destination register group is legal. Otherwise, it is illegal.
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multiclass VPseudoBinaryW_VV {
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foreach m = MxListW.m in
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foreach m = MxListW in
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defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
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"@earlyclobber $rd">;
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}
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multiclass VPseudoBinaryW_VX {
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foreach m = MxListW.m in
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foreach m = MxListW in
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defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
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"@earlyclobber $rd">;
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}
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multiclass VPseudoBinaryW_VF {
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foreach m = MxListW.m in
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foreach f = FPListW.fpinfo in
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foreach m = MxListW in
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foreach f = FPListW in
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defm "_V" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass,
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f.fprclass, m,
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"@earlyclobber $rd">;
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}
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multiclass VPseudoBinaryW_WV {
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foreach m = MxListW.m in {
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foreach m = MxListW in {
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defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
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"@earlyclobber $rd">;
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defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,
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@ -1692,13 +1683,13 @@ multiclass VPseudoBinaryW_WV {
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}
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multiclass VPseudoBinaryW_WX {
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foreach m = MxListW.m in
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foreach m = MxListW in
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defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
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}
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multiclass VPseudoBinaryW_WF {
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foreach m = MxListW.m in
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foreach f = FPListW.fpinfo in
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foreach m = MxListW in
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foreach f = FPListW in
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defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
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f.fprclass, m>;
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}
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@ -1709,19 +1700,19 @@ multiclass VPseudoBinaryW_WF {
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// "The destination EEW is smaller than the source EEW and the overlap is in the
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// lowest-numbered part of the source register group."
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multiclass VPseudoBinaryV_WV {
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foreach m = MxListW.m in
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foreach m = MxListW in
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defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
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!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
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}
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multiclass VPseudoBinaryV_WX {
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foreach m = MxListW.m in
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foreach m = MxListW in
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defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
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!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
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}
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multiclass VPseudoBinaryV_WI {
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foreach m = MxListW.m in
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foreach m = MxListW in
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defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
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!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
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}
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@ -1731,7 +1722,7 @@ multiclass VPseudoBinaryV_WI {
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// For vadc and vsbc, CarryIn == 1 and CarryOut == 0
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multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(CarryOut, VR,
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!if(!and(CarryIn, !not(CarryOut)),
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@ -1741,7 +1732,7 @@ multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
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multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(CarryOut, VR,
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!if(!and(CarryIn, !not(CarryOut)),
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@ -1750,8 +1741,8 @@ multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
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}
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multiclass VPseudoVMRG_FM {
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foreach m = MxList.m in
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foreach f = FPList.fpinfo in
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foreach m = MxList in
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foreach f = FPList in
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def "_V" # f.FX # "M_" # m.MX :
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VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
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m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
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@ -1760,7 +1751,7 @@ multiclass VPseudoVMRG_FM {
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multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = ""> {
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foreach m = MxList.m in
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foreach m = MxList in
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def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(CarryOut, VR,
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!if(!and(CarryIn, !not(CarryOut)),
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@ -1769,7 +1760,7 @@ multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
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}
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multiclass VPseudoUnaryVMV_V_X_I {
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in {
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def "_V_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, m.vrclass>,
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Sched<[WriteVIMovV, ReadVIMovV]>;
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@ -1782,8 +1773,8 @@ multiclass VPseudoUnaryVMV_V_X_I {
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}
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multiclass VPseudoVMV_F {
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foreach m = MxList.m in {
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foreach f = FPList.fpinfo in {
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foreach m = MxList in {
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foreach f = FPList in {
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let VLMul = m.value in {
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def "_" # f.FX # "_" # m.MX :
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VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>,
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@ -1794,7 +1785,7 @@ multiclass VPseudoVMV_F {
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}
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multiclass VPseudoVCLS_V {
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in {
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def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
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Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>;
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@ -1805,7 +1796,7 @@ multiclass VPseudoVCLS_V {
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}
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multiclass VPseudoVSQR_V {
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in {
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def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
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Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>;
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@ -1816,7 +1807,7 @@ multiclass VPseudoVSQR_V {
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}
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multiclass VPseudoVRCP_V {
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foreach m = MxList.m in {
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foreach m = MxList in {
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let VLMul = m.value in {
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def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
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Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>;
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@ -1828,7 +1819,7 @@ multiclass VPseudoVRCP_V {
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multiclass PseudoVEXT_VF2 {
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defvar constraints = "@earlyclobber $rd";
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foreach m = MxListVF2.m in
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foreach m = MxListVF2 in
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{
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let VLMul = m.value in {
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def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
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@ -1842,7 +1833,7 @@ multiclass PseudoVEXT_VF2 {
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multiclass PseudoVEXT_VF4 {
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defvar constraints = "@earlyclobber $rd";
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foreach m = MxListVF4.m in
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foreach m = MxListVF4 in
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{
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let VLMul = m.value in {
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def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
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@ -1856,7 +1847,7 @@ multiclass PseudoVEXT_VF4 {
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multiclass PseudoVEXT_VF8 {
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defvar constraints = "@earlyclobber $rd";
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foreach m = MxListVF8.m in
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foreach m = MxListVF8 in
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{
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let VLMul = m.value in {
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def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
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@ -1880,28 +1871,28 @@ multiclass PseudoVEXT_VF8 {
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// With LMUL<=1 the source and dest occupy a single register so any overlap
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// is in the lowest-numbered part.
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multiclass VPseudoBinaryM_VV {
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foreach m = MxList.m in
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foreach m = MxList in
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defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
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!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
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}
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multiclass VPseudoBinaryM_VX {
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foreach m = MxList.m in
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foreach m = MxList in
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defm "_VX" :
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VPseudoBinaryM<VR, m.vrclass, GPR, m,
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!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
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}
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multiclass VPseudoBinaryM_VF {
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foreach m = MxList.m in
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foreach f = FPList.fpinfo in
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foreach m = MxList in
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foreach f = FPList in
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defm "_V" # f.FX :
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VPseudoBinaryM<VR, m.vrclass, f.fprclass, m,
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!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
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}
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multiclass VPseudoBinaryM_VI {
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foreach m = MxList.m in
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foreach m = MxList in
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defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
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!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
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}
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@ -2200,26 +2191,26 @@ multiclass VPseudoTernaryWithPolicy<VReg RetClass,
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}
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multiclass VPseudoTernaryV_VV_AAXA<string Constraint = ""> {
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foreach m = MxList.m in {
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foreach m = MxList in {
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defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
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Constraint, /*Commutable*/1>;
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}
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}
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multiclass VPseudoTernaryV_VX<string Constraint = ""> {
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foreach m = MxList.m in
|
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foreach m = MxList in
|
||||
defm _VX : VPseudoTernary<m.vrclass, m.vrclass, GPR, m, Constraint>;
|
||||
}
|
||||
|
||||
multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> {
|
||||
foreach m = MxList.m in
|
||||
foreach m = MxList in
|
||||
defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
|
||||
Constraint, /*Commutable*/1>;
|
||||
}
|
||||
|
||||
multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> {
|
||||
foreach m = MxList.m in
|
||||
foreach f = FPList.fpinfo in
|
||||
foreach m = MxList in
|
||||
foreach f = FPList in
|
||||
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass,
|
||||
m.vrclass, m, Constraint,
|
||||
/*Commutable*/1>;
|
||||
|
|
@ -2227,28 +2218,28 @@ multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> {
|
|||
|
||||
multiclass VPseudoTernaryW_VV {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxListW.m in
|
||||
foreach m = MxListW in
|
||||
defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
|
||||
constraint>;
|
||||
}
|
||||
|
||||
multiclass VPseudoTernaryW_VX {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxListW.m in
|
||||
foreach m = MxListW in
|
||||
defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m,
|
||||
constraint>;
|
||||
}
|
||||
|
||||
multiclass VPseudoTernaryW_VF {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxListW.m in
|
||||
foreach f = FPListW.fpinfo in
|
||||
foreach m = MxListW in
|
||||
foreach f = FPListW in
|
||||
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
|
||||
m.vrclass, m, constraint>;
|
||||
}
|
||||
|
||||
multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
|
||||
foreach m = MxList.m in
|
||||
foreach m = MxList in
|
||||
defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
|
||||
}
|
||||
|
||||
|
|
@ -2328,35 +2319,35 @@ multiclass VPseudoVCMPM_VX_VI {
|
|||
}
|
||||
|
||||
multiclass VPseudoVRED_VS {
|
||||
foreach m = MxList.m in {
|
||||
foreach m = MxList in {
|
||||
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
|
||||
Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV, ReadVIRedV, ReadVMask]>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VPseudoVWRED_VS {
|
||||
foreach m = MxList.m in {
|
||||
foreach m = MxList in {
|
||||
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
|
||||
Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVMask]>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VPseudoVFRED_VS {
|
||||
foreach m = MxList.m in {
|
||||
foreach m = MxList in {
|
||||
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
|
||||
Sched<[WriteVFRedV, ReadVFRedV, ReadVFRedV, ReadVFRedV, ReadVMask]>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VPseudoVFREDO_VS {
|
||||
foreach m = MxList.m in {
|
||||
foreach m = MxList in {
|
||||
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
|
||||
Sched<[WriteVFRedOV, ReadVFRedOV, ReadVFRedOV, ReadVFRedOV, ReadVMask]>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VPseudoVFWRED_VS {
|
||||
foreach m = MxList.m in {
|
||||
foreach m = MxList in {
|
||||
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
|
||||
Sched<[WriteVFWRedV, ReadVFWRedV, ReadVFWRedV, ReadVFWRedV, ReadVMask]>;
|
||||
}
|
||||
|
|
@ -2374,61 +2365,61 @@ multiclass VPseudoConversion<VReg RetClass,
|
|||
}
|
||||
|
||||
multiclass VPseudoVCVTI_V {
|
||||
foreach m = MxList.m in
|
||||
foreach m = MxList in
|
||||
defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
|
||||
Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVCVTF_V {
|
||||
foreach m = MxList.m in
|
||||
foreach m = MxList in
|
||||
defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
|
||||
Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoConversionW_V {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxListW.m in
|
||||
foreach m = MxListW in
|
||||
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVWCVTI_V {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxList.m[0-5] in
|
||||
foreach m = MxList[0-5] in
|
||||
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
|
||||
Sched<[WriteVFWCvtFToIV, ReadVFWCvtFToIV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVWCVTF_V {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxList.m[0-5] in
|
||||
foreach m = MxList[0-5] in
|
||||
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
|
||||
Sched<[WriteVFWCvtIToFV, ReadVFWCvtIToFV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVWCVTD_V {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxList.m[0-5] in
|
||||
foreach m = MxList[0-5] in
|
||||
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
|
||||
Sched<[WriteVFWCvtFToFV, ReadVFWCvtFToFV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVNCVTI_W {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxList.m[0-5] in
|
||||
foreach m = MxList[0-5] in
|
||||
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
|
||||
Sched<[WriteVFNCvtFToIV, ReadVFNCvtFToIV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVNCVTF_W {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxList.m[0-5] in
|
||||
foreach m = MxList[0-5] in
|
||||
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
|
||||
Sched<[WriteVFNCvtIToFV, ReadVFNCvtIToFV, ReadVMask]>;
|
||||
}
|
||||
|
||||
multiclass VPseudoVNCVTD_W {
|
||||
defvar constraint = "@earlyclobber $rd";
|
||||
foreach m = MxListW.m in
|
||||
foreach m = MxListW in
|
||||
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
|
||||
Sched<[WriteVFNCvtFToFV, ReadVFNCvtFToFV, ReadVMask]>;
|
||||
}
|
||||
|
|
@ -3782,7 +3773,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1 in {
|
|||
def PseudoVRELOAD_M8 : VPseudo<VL8RE8_V, V_M8, (outs VRM8:$rs1), (ins GPR:$rs2)>;
|
||||
}
|
||||
|
||||
foreach lmul = MxList.m in {
|
||||
foreach lmul = MxList in {
|
||||
foreach nf = NFSet<lmul>.L in {
|
||||
defvar vreg = SegRegClass<lmul, nf>.RC;
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in {
|
||||
|
|
@ -4345,7 +4336,7 @@ defm PseudoVID : VPseudoVID_V;
|
|||
|
||||
let Predicates = [HasVInstructions] in {
|
||||
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
|
||||
foreach m = MxList.m in {
|
||||
foreach m = MxList in {
|
||||
let VLMul = m.value in {
|
||||
let HasSEWOp = 1, BaseInstr = VMV_X_S in
|
||||
def PseudoVMV_X_S # "_" # m.MX:
|
||||
|
|
@ -4371,8 +4362,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
|
|||
|
||||
let Predicates = [HasVInstructionsAnyF] in {
|
||||
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
|
||||
foreach m = MxList.m in {
|
||||
foreach f = FPList.fpinfo in {
|
||||
foreach m = MxList in {
|
||||
foreach f = FPList in {
|
||||
let VLMul = m.value in {
|
||||
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
|
||||
def "PseudoVFMV_" # f.FX # "_S_" # m.MX :
|
||||
|
|
|
|||
Loading…
Reference in New Issue