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Simplify FastISel's constructor by giving it a FunctionLoweringInfo 

instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.

llvm-svn: 107789
This commit is contained in:
Dan Gohman 2010-07-07 16:29:44 +00:00
parent 3e2ee147d0
commit 87fb4e8fcd
7 changed files with 51 additions and 145 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
llvm/include/llvm/CodeGen/FastISel.h
View File

@ -24,6 +24,7 @@ namespace llvm {
class AllocaInst;
class ConstantFP;
class FunctionLoweringInfo;
class Instruction;
class MachineBasicBlock;
class MachineConstantPool;
@ -45,14 +46,7 @@ class FastISel {
protected:
MachineBasicBlock *MBB;
DenseMap<const Value *, unsigned> LocalValueMap;
DenseMap<const Value *, unsigned> &ValueMap;
DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
DenseMap<const AllocaInst *, int> &StaticAllocaMap;
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate;
#ifndef NDEBUG
SmallSet<const Instruction *, 8> &CatchInfoLost;
#endif
MachineFunction &MF;
FunctionLoweringInfo &FuncInfo;
MachineRegisterInfo &MRI;
MachineFrameInfo &MFI;
MachineConstantPool &MCP;
@ -113,15 +107,7 @@ public:
virtual ~FastISel();
protected:
FastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am,
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &cil
#endif
);
explicit FastISel(FunctionLoweringInfo &funcInfo);
/// TargetSelectInstruction - This method is called by target-independent
/// code when the normal FastISel process fails to select an instruction.

12
llvm/include/llvm/Target/TargetLowering.h
View File

@ -43,6 +43,7 @@ namespace llvm {
class CallInst;
class Function;
class FastISel;
class FunctionLoweringInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineFrameInfo;
@ -1223,16 +1224,7 @@ public:
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
virtual FastISel *
createFastISel(MachineFunction &,
DenseMap<const Value *, unsigned> &,
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
DenseMap<const AllocaInst *, int> &,
std::vector<std::pair<MachineInstr*, unsigned> > &
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &CatchInfoLost
#endif
) const {
virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
return 0;
}

66
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -100,8 +100,8 @@ unsigned FastISel::getRegForValue(const Value *V) {
// cache values defined by Instructions across blocks, and other values
// only locally. This is because Instructions already have the SSA
// def-dominates-use requirement enforced.
DenseMap<const Value *, unsigned>::iterator I = ValueMap.find(V);
if (I != ValueMap.end())
DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
if (I != FuncInfo.ValueMap.end())
return I->second;
unsigned Reg = LocalValueMap[V];
if (Reg != 0)
@ -112,7 +112,7 @@ unsigned FastISel::getRegForValue(const Value *V) {
if (IsBottomUp) {
Reg = createResultReg(TLI.getRegClassFor(VT));
if (isa<Instruction>(V))
ValueMap[V] = Reg;
FuncInfo.ValueMap[V] = Reg;
else
LocalValueMap[V] = Reg;
return Reg;
@ -189,8 +189,8 @@ unsigned FastISel::lookUpRegForValue(const Value *V) {
// cache values defined by Instructions across blocks, and other values
// only locally. This is because Instructions already have the SSA
// def-dominates-use requirement enforced.
DenseMap<const Value *, unsigned>::iterator I = ValueMap.find(V);
if (I != ValueMap.end())
DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
if (I != FuncInfo.ValueMap.end())
return I->second;
return LocalValueMap[V];
}
@ -207,7 +207,7 @@ unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) {
return Reg;
}
unsigned &AssignedReg = ValueMap[I];
unsigned &AssignedReg = FuncInfo.ValueMap[I];
if (AssignedReg == 0)
AssignedReg = Reg;
else if (Reg != AssignedReg) {
@ -400,7 +400,7 @@ bool FastISel::SelectCall(const User *I) {
case Intrinsic::dbg_declare: {
const DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
if (!DIVariable(DI->getVariable()).Verify() ||
!MF.getMMI().hasDebugInfo())
!FuncInfo.MF->getMMI().hasDebugInfo())
return true;
const Value *Address = DI->getAddress();
@ -414,11 +414,12 @@ bool FastISel::SelectCall(const User *I) {
// those are handled in SelectionDAGBuilder.
if (AI) {
DenseMap<const AllocaInst*, int>::iterator SI =
StaticAllocaMap.find(AI);
if (SI == StaticAllocaMap.end()) break; // VLAs.
FuncInfo.StaticAllocaMap.find(AI);
if (SI == FuncInfo.StaticAllocaMap.end()) break; // VLAs.
int FI = SI->second;
if (!DI->getDebugLoc().isUnknown())
MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc());
FuncInfo.MF->getMMI().setVariableDbgInfo(DI->getVariable(),
FI, DI->getDebugLoc());
} else
// Building the map above is target independent. Generating DBG_VALUE
// inline is target dependent; do this now.
@ -478,10 +479,10 @@ bool FastISel::SelectCall(const User *I) {
default: break;
case TargetLowering::Expand: {
if (MBB->isLandingPad())
AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB);
AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), MBB);
else {
#ifndef NDEBUG
CatchInfoLost.insert(cast<CallInst>(I));
FuncInfo.CatchInfoLost.insert(cast<CallInst>(I));
#endif
// FIXME: Mark exception selector register as live in. Hack for PR1508.
unsigned Reg = TLI.getExceptionSelectorRegister();
@ -790,7 +791,7 @@ FastISel::SelectOperator(const User *I, unsigned Opcode) {
if (BI->isUnconditional()) {
const BasicBlock *LLVMSucc = BI->getSuccessor(0);
MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
FastEmitBranch(MSucc, BI->getDebugLoc());
return true;
}
@ -806,7 +807,7 @@ FastISel::SelectOperator(const User *I, unsigned Opcode) {
case Instruction::Alloca:
// FunctionLowering has the static-sized case covered.
if (StaticAllocaMap.count(cast<AllocaInst>(I)))
if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
return true;
// Dynamic-sized alloca is not handled yet.
@ -852,28 +853,13 @@ FastISel::SelectOperator(const User *I, unsigned Opcode) {
}
}
FastISel::FastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am,
std::vector<std::pair<MachineInstr*, unsigned> > &pn
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &cil
#endif
)
FastISel::FastISel(FunctionLoweringInfo &funcInfo)
: MBB(0),
ValueMap(vm),
MBBMap(bm),
StaticAllocaMap(am),
PHINodesToUpdate(pn),
#ifndef NDEBUG
CatchInfoLost(cil),
#endif
MF(mf),
MRI(MF.getRegInfo()),
MFI(*MF.getFrameInfo()),
MCP(*MF.getConstantPool()),
TM(MF.getTarget()),
FuncInfo(funcInfo),
MRI(FuncInfo.MF->getRegInfo()),
MFI(*FuncInfo.MF->getFrameInfo()),
MCP(*FuncInfo.MF->getConstantPool()),
TM(FuncInfo.MF->getTarget()),
TD(*TM.getTargetData()),
TII(*TM.getInstrInfo()),
TLI(*TM.getTargetLowering()),
@ -1183,14 +1169,14 @@ bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
const TerminatorInst *TI = LLVMBB->getTerminator();
SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
unsigned OrigNumPHINodesToUpdate = PHINodesToUpdate.size();
unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
// Check successor nodes' PHI nodes that expect a constant to be available
// from this block.
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
const BasicBlock *SuccBB = TI->getSuccessor(succ);
if (!isa<PHINode>(SuccBB->begin())) continue;
MachineBasicBlock *SuccMBB = MBBMap[SuccBB];
MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
// If this terminator has multiple identical successors (common for
// switches), only handle each succ once.
@ -1219,7 +1205,7 @@ bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
else {
PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
return false;
}
}
@ -1234,10 +1220,10 @@ bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
unsigned Reg = getRegForValue(PHIOp);
if (Reg == 0) {
PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
return false;
}
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
DL = DebugLoc();
}
}

8
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -671,13 +671,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
// Initialize the Fast-ISel state, if needed.
FastISel *FastIS = 0;
if (EnableFastISel)
FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
FuncInfo->StaticAllocaMap,
FuncInfo->PHINodesToUpdate
#ifndef NDEBUG
, FuncInfo->CatchInfoLost
#endif
);
FastIS = TLI.createFastISel(*FuncInfo);
// Iterate over all basic blocks in the function.
for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {

53
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@ -52,20 +53,7 @@ class X86FastISel : public FastISel {
bool X86ScalarSSEf32;
public:
explicit X86FastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am,
std::vector<std::pair<MachineInstr*, unsigned> > &pn
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &cil
#endif
)
: FastISel(mf, vm, bm, am, pn
#ifndef NDEBUG
, cil
#endif
) {
explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
X86ScalarSSEf64 = Subtarget->hasSSE2();
@ -345,7 +333,7 @@ bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
// Don't walk into other basic blocks; it's possible we haven't
// visited them yet, so the instructions may not yet be assigned
// virtual registers.
if (MBBMap[I->getParent()] != MBB)
if (FuncInfo.MBBMap[I->getParent()] != MBB)
return false;
Opcode = I->getOpcode();
@ -382,8 +370,9 @@ bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
case Instruction::Alloca: {
// Do static allocas.
const AllocaInst *A = cast<AllocaInst>(V);
DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
if (SI != StaticAllocaMap.end()) {
DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(A);
if (SI != FuncInfo.StaticAllocaMap.end()) {
AM.BaseType = X86AddressMode::FrameIndexBase;
AM.Base.FrameIndex = SI->second;
return true;
@ -498,7 +487,7 @@ bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
// If this reference is relative to the pic base, set it now.
if (isGlobalRelativeToPICBase(GVFlags)) {
// FIXME: How do we know Base.Reg is free??
AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
}
// Unless the ABI requires an extra load, return a direct reference to
@ -844,8 +833,8 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
// Unconditional branches are selected by tablegen-generated code.
// Handle a conditional branch.
const BranchInst *BI = cast<BranchInst>(I);
MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
// Fold the common case of a conditional branch with a comparison.
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
@ -1511,7 +1500,7 @@ bool X86FastISel::X86SelectCall(const Instruction *I) {
// GOT pointer.
if (Subtarget->isPICStyleGOT()) {
TargetRegisterClass *RC = X86::GR32RegisterClass;
unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
DL);
assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
@ -1758,10 +1747,10 @@ unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
unsigned char OpFlag = 0;
if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
OpFlag = X86II::MO_PIC_BASE_OFFSET;
PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
} else if (Subtarget->isPICStyleGOT()) {
OpFlag = X86II::MO_GOTOFF;
PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
} else if (Subtarget->isPICStyleRIPRel() &&
TM.getCodeModel() == CodeModel::Small) {
PICBase = X86::RIP;
@ -1784,7 +1773,7 @@ unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
// various places, but TargetMaterializeAlloca also needs a check
// in order to avoid recursion between getRegForValue,
// X86SelectAddrss, and TargetMaterializeAlloca.
if (!StaticAllocaMap.count(C))
if (!FuncInfo.StaticAllocaMap.count(C))
return 0;
X86AddressMode AM;
@ -1798,19 +1787,7 @@ unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
}
namespace llvm {
llvm::FastISel *X86::createFastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am,
std::vector<std::pair<MachineInstr*, unsigned> > &pn
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &cil
#endif
) {
return new X86FastISel(mf, vm, bm, am, pn
#ifndef NDEBUG
, cil
#endif
);
llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
return new X86FastISel(funcInfo);
}
}

16
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -2471,20 +2471,8 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
}
FastISel *
X86TargetLowering::createFastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
DenseMap<const AllocaInst *, int> &am,
std::vector<std::pair<MachineInstr*, unsigned> > &pn
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &cil
#endif
) const {
return X86::createFastISel(mf, vm, bm, am, pn
#ifndef NDEBUG
, cil
#endif
);
X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
return X86::createFastISel(funcInfo);
}

21
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -579,16 +579,7 @@ namespace llvm {
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
virtual FastISel *
createFastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &,
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
DenseMap<const AllocaInst *, int> &,
std::vector<std::pair<MachineInstr*, unsigned> > &
#ifndef NDEBUG
, SmallSet<const Instruction *, 8> &
#endif
) const;
virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
@ -821,15 +812,7 @@ namespace llvm {
};
namespace X86 {
FastISel *createFastISel(MachineFunction &mf,
DenseMap<const Value *, unsigned> &,
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
DenseMap<const AllocaInst *, int> &,
std::vector<std::pair<MachineInstr*, unsigned> > &
#ifndef NDEBUG
, SmallSet<const Instruction*, 8> &
#endif
);
FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
}
}