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[PowerPC] Basic support for P9 byte comparison and count trailing zero insns 

This patch corresponds to review:
http://reviews.llvm.org/D17850

This patch implements the following instructions:
cmprb, cmpeqb, cnttzw, cnttzw., cnttzd, cnttzd.

llvm-svn: 266228
This commit is contained in:
Nemanja Ivanovic 2016-04-13 18:51:18 +00:00
parent 9df0720766
commit 87bcae366d
7 changed files with 111 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
llvm/lib/Target/PowerPC/PPC.td
View File

@ -122,12 +122,6 @@ def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
"Enable POWER8 vector instructions",
[FeatureVSX, FeatureP8Altivec]>;
def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
"Enable POWER9 Altivec instructions",
[FeatureP8Altivec]>;
def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
"Enable POWER9 vector instructions",
[FeatureP8Vector, FeatureP9Altivec]>;
def FeatureDirectMove :
SubtargetFeature<"direct-move", "HasDirectMove", "true",
"Enable Power8 direct move instructions",
@ -149,7 +143,6 @@ def FeatureFloat128 :
SubtargetFeature<"float128", "HasFloat128", "true",
"Enable the __float128 data type for IEEE-754R Binary128.",
[FeatureVSX]>;
def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD",
"POPCNTD_Fast",
"Enable the popcnt[dw] instructions">;
@ -166,6 +159,13 @@ def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
"true",
"Enable instructions added in ISA 3.0.">;
def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
"Enable POWER9 Altivec instructions",
[FeatureISA3_0, FeatureP8Altivec]>;
def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
"Enable POWER9 vector instructions",
[FeatureISA3_0, FeatureP8Vector,
FeatureP9Altivec]>;
/* Since new processors generally contain a superset of features of those that
came before them, the idea is to make implementations of new processors
@ -198,6 +198,8 @@ def ProcessorFeatures {
FeatureFusion];
list<SubtargetFeature> Power8FeatureList =
!listconcat(Power7FeatureList, Power8SpecificFeatures);
list<SubtargetFeature> Power9SpecificFeatures =
[FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
}
// Note: Future features to add when support is extended to more

16
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -574,6 +574,14 @@ let isCompare = 1, hasSideEffects = 0 in {
def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"cmpldi $dst, $src1, $src2",
IIC_IntCompare>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
(ins u1imm:$L, g8rc:$rA, g8rc:$rB),
"cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
Requires<[IsISA3_0]>;
def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF),
(ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB",
IIC_IntCompare, []>, Requires<[IsISA3_0]>;
}
let hasSideEffects = 0 in {
@ -590,6 +598,9 @@ defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
"cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzw", "$rA, $rS", IIC_IntGeneral, []>,
Requires<[IsISA3_0]>;
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
"extsb", "$rA, $rS", IIC_IntSimple,
@ -623,9 +634,12 @@ defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
"sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
"cntlzd", "$rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (ctlz i64:$rS))]>;
defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzd", "$rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
"popcntd $rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (ctpop i64:$rS))]>;

37
llvm/lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -785,6 +785,43 @@ class X_RT5_RA5_RB5<bits<10> xo, string opc, RegisterOperand type,
: XForm_base_r3xo<31, xo, (outs type:$rD), (ins type:$rA, type:$rB),
!strconcat(opc, " $rD, $rA, $rB"), itin, pattern>;
class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
bits<3> BF;
bits<1> L;
bits<5> RA;
bits<5> RB;
let Pattern = pattern;
let Inst{6-8} = BF;
let Inst{9} = 0;
let Inst{10} = L;
let Inst{11-15} = RA;
let Inst{16-20} = RB;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
// Same as XForm_17 but with GPR's and new naming convention
class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
bits<3> BF;
bits<5> RA;
bits<5> RB;
let Pattern = pattern;
let Inst{6-8} = BF;
let Inst{9-10} = 0;
let Inst{11-15} = RA;
let Inst{16-20} = RB;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>

7
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1997,6 +1997,10 @@ let isCompare = 1, hasSideEffects = 0 in {
"cmpwi $crD, $rA, $imm", IIC_IntCompare>;
def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
"cmplwi $dst, $src1, $src2", IIC_IntCompare>;
def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
(ins u1imm:$L, g8rc:$rA, g8rc:$rB),
"cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
Requires<[IsISA3_0]>;
}
}
@ -2050,6 +2054,9 @@ defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
"cntlzw", "$rA, $rS", IIC_IntGeneral,
[(set i32:$rA, (ctlz i32:$rS))]>;
defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
"cnttzw", "$rA, $rS", IIC_IntGeneral,
[(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
"extsb", "$rA, $rS", IIC_IntSimple,
[(set i32:$rA, (sext_inreg i32:$rS, i8))]>;

7
llvm/lib/Target/PowerPC/README_P9.txt
View File

@ -373,6 +373,13 @@ VSX:
. Provide builtin?
(set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB))
Fixed Point Facility:
- Exploit cmprb and cmpeqb (perhaps for something like
isalpha/isdigit/isupper/islower and isspace respectivelly). This can
perhaps be done through a builtin.
- Provide testing for cnttz[dw]
- Insert Exponent DP/QP: xsiexpdp xsiexpqp
. Use intrinsic?
. xsiexpdp:

18
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
View File

@ -418,6 +418,24 @@
# CHECK: cmplw 2, 3, 4
0x7d 0x03 0x20 0x40
# CHECK: cmprb 3, 1, 7, 17
0x7d 0xa7 0x89 0x80
# CHECK: cmpeqb 3, 7, 17
0x7d 0x87 0x89 0xc0
# CHECK: cnttzw 7, 17
0x7e 0x27 0x04 0x34
# CHECK: cnttzw. 7, 17
0x7e 0x27 0x04 0x35
# CHECK: cnttzd 7, 17
0x7e 0x27 0x04 0x74
# CHECK: cnttzd. 7, 17
0x7e 0x27 0x04 0x75
# CHECK: twllti 3, 4
0x0c 0x43 0x00 0x04

18
llvm/test/MC/PowerPC/ppc64-encoding.s
View File

@ -533,6 +533,24 @@
# CHECK-BE: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
# CHECK-LE: cmplw 2, 3, 4 # encoding: [0x40,0x20,0x03,0x7d]
cmpl 2, 0, 3, 4
# CHECK-BE: cmprb 3, 1, 7, 17 # encoding: [0x7d,0xa7,0x89,0x80]
# CHECK-LE: cmprb 3, 1, 7, 17 # encoding: [0x80,0x89,0xa7,0x7d]
cmprb 3, 1, 7, 17
# CHECK-BE: cmpeqb 3, 7, 17 # encoding: [0x7d,0x87,0x89,0xc0]
# CHECK-LE: cmpeqb 3, 7, 17 # encoding: [0xc0,0x89,0x87,0x7d]
cmpeqb 3, 7, 17
# CHECK-BE: cnttzw 7, 17 # encoding: [0x7e,0x27,0x04,0x34]
# CHECK-LE: cnttzw 7, 17 # encoding: [0x34,0x04,0x27,0x7e]
cnttzw 7, 17
# CHECK-BE: cnttzw. 7, 17 # encoding: [0x7e,0x27,0x04,0x35]
# CHECK-LE: cnttzw. 7, 17 # encoding: [0x35,0x04,0x27,0x7e]
cnttzw. 7, 17
# CHECK-BE: cnttzd 7, 17 # encoding: [0x7e,0x27,0x04,0x74]
# CHECK-LE: cnttzd 7, 17 # encoding: [0x74,0x04,0x27,0x7e]
cnttzd 7, 17
# CHECK-BE: cnttzd. 7, 17 # encoding: [0x7e,0x27,0x04,0x75]
# CHECK-LE: cnttzd. 7, 17 # encoding: [0x75,0x04,0x27,0x7e]
cnttzd. 7, 17
# Fixed-point trap instructions