Allow target to specify register output dependency. Still default to one.

llvm-svn: 146547

llvm/include/llvm/Target/TargetInstrInfo.h

@@ -648,6 +648,16 @@ public:
                                 SDNode *DefNode, unsigned DefIdx,
                                 SDNode *UseNode, unsigned UseIdx) const;
 
+  /// getOutputLatency - Compute and return the output dependency latency of a
+  /// a given pair of defs which both target the same register. This is usually
+  /// one.
+  virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
+                                    const MachineInstr *DefMI1,
+                                    const MachineInstr *DefMI2,
+                                    unsigned Reg) const {
+    return 1;
+  }
+
   /// getInstrLatency - Compute the instruction latency of a given instruction.
   /// If the instruction has higher cost when predicated, it's returned via
   /// PredCost.

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

@@ -278,7 +278,13 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
         if (DefSU != SU &&
             (Kind != SDep::Output || !MO.isDead() ||
              !DefSU->getInstr()->registerDefIsDead(Reg))) {
-          DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
+          if (Kind == SDep::Anti)
+            DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
+          else {
+            unsigned AOLat = TII->getOutputLatency(InstrItins, MI,
+                                                   DefSU->getInstr(), Reg);
+            DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
+          }
         }
       }
       for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {