From 87975df580ccf7ffc73d86dafd52daa662b2c71d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 14 Dec 2011 02:28:53 +0000 Subject: [PATCH] Allow target to specify register output dependency. Still default to one. llvm-svn: 146547 --- llvm/include/llvm/Target/TargetInstrInfo.h | 10 ++++++++++ llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 8 +++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h index 1903da73e6a6..957a89af8209 100644 --- a/llvm/include/llvm/Target/TargetInstrInfo.h +++ b/llvm/include/llvm/Target/TargetInstrInfo.h @@ -648,6 +648,16 @@ public: SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const; + /// getOutputLatency - Compute and return the output dependency latency of a + /// a given pair of defs which both target the same register. This is usually + /// one. + virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, + const MachineInstr *DefMI1, + const MachineInstr *DefMI2, + unsigned Reg) const { + return 1; + } + /// getInstrLatency - Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via /// PredCost. diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index aedc2a13fafe..47c533932d69 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -278,7 +278,13 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) { if (DefSU != SU && (Kind != SDep::Output || !MO.isDead() || !DefSU->getInstr()->registerDefIsDead(Reg))) { - DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg)); + if (Kind == SDep::Anti) + DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg)); + else { + unsigned AOLat = TII->getOutputLatency(InstrItins, MI, + DefSU->getInstr(), Reg); + DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg)); + } } } for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {