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Allow target to specify register output dependency. Still default to one. 

llvm-svn: 146547
This commit is contained in:
Evan Cheng 2011-12-14 02:28:53 +00:00
parent 2be88f1301
commit 87975df580
2 changed files with 17 additions and 1 deletions
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10
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -648,6 +648,16 @@ public:
SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const;
/// getOutputLatency - Compute and return the output dependency latency of a
/// a given pair of defs which both target the same register. This is usually
/// one.
virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI1,
const MachineInstr *DefMI2,
unsigned Reg) const {
return 1;
}
/// getInstrLatency - Compute the instruction latency of a given instruction.
/// If the instruction has higher cost when predicated, it's returned via
/// PredCost.

8
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -278,7 +278,13 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
if (DefSU != SU &&
(Kind != SDep::Output || !MO.isDead() ||
!DefSU->getInstr()->registerDefIsDead(Reg))) {
DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
if (Kind == SDep::Anti)
DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
else {
unsigned AOLat = TII->getOutputLatency(InstrItins, MI,
DefSU->getInstr(), Reg);
DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
}
}
}
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {