forked from OSchip/llvm-project
[ARM,AArch64] NFC. Add extra test cases for bswap lowering.
These tests were sitting in Phab for many months. They're good tests and should be in. Patch by Charlie Turner. llvm-svn: 269425
This commit is contained in:
Renato Golin
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24dbd2e760
commit
8793c521bc
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@ -0,0 +1,39 @@
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; RUN: llc -march=aarch64 < %s | FileCheck %s
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; Test byte swap instrinsic lowering on AArch64 targets.
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define i16 @bswap16(i16 %x) #0 {
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%1 = tail call i16 @llvm.bswap.i16(i16 %x)
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ret i16 %1
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; CHECK-LABEL: bswap16
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; CHECK: rev [[R0:w[0-9]+]], {{w[0-9]+}}
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; CHECK-NEXT: lsr {{w[0-9]+}}, [[R0]], #16
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}
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define i32 @bswap32(i32 %x) #0 {
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%1 = tail call i32 @llvm.bswap.i32(i32 %x)
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ret i32 %1
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; CHECK-LABEL: bswap32
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; CHECK: rev [[R0:w[0-9]+]], [[R0]]
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}
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define i48 @bswap48(i48 %x) #0 {
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%1 = tail call i48 @llvm.bswap.i48(i48 %x)
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ret i48 %1
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; CHECK-LABEL: bswap48
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; CHECK: rev [[R0:x[0-9]+]], {{x[0-9]+}}
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; CHECK-NEXT: lsr {{x[0-9]+}}, [[R0]], #16
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}
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define i64 @bswap64(i64 %x) #0 {
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%1 = tail call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %1
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; CHECK-LABEL: bswap64
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; CHECK: rev [[R0:x[0-9]+]], [[R0]]
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; CHECK-NOT: rev
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}
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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declare i48 @llvm.bswap.i48(i48)
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declare i64 @llvm.bswap.i64(i64)
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@ -0,0 +1,145 @@
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; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck -check-prefix PRE6 %s
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; RUN: llc -march=armeb -mattr=+v4t < %s | FileCheck -check-prefix PRE6BE %s
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; RUN: llc -march=arm -mattr=+v5t < %s | FileCheck -check-prefix PRE6 %s
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; RUN: llc -march=arm -mattr=+v5te < %s | FileCheck -check-prefix PRE6 %s
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; RUN: llc -march=arm -mattr=+v6 < %s | FileCheck -check-prefix REV %s
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; RUN: llc -march=armeb -mattr=+v6 < %s | FileCheck -check-prefix REVBE %s
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; RUN: llc -march=arm -mattr=+v6k < %s | FileCheck -check-prefix REV %s
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; RUN: llc -march=arm -mattr=+v6m < %s | FileCheck -check-prefix REV %s
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; RUN: llc -march=arm -mattr=+v6t2 < %s | FileCheck -check-prefix REV %s
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; RUN: llc -march=arm -mattr=+v7 < %s | FileCheck -check-prefix REV %s
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; RUN: llc -march=arm -mattr=+v8 < %s | FileCheck -check-prefix REV %s
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; RUN: llc -march=arm -mattr=+v8.1a < %s | FileCheck -check-prefix REV %s
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;; Test byte swap instrinsic lowering on ARM targets.
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;; The REV instruction only appeared in ARMv6 and later. Earlier
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;; supported architecture have to open-code this intrinsic.
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define i16 @bswap16(i16 %x) #0 {
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%1 = tail call i16 @llvm.bswap.i16(i16 %x)
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ret i16 %1
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; PRE6-LABEL: bswap16
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;; The source register patterns are all capable of matching a new
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;; register to avoid specifying allocation choices unnecessarily.
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; PRE6: mov [[R1:r[0-9]+|lr]], #16711680
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; PRE6-NEXT: and [[R2:r[0-9]+|lr]], [[R1]], [[R0:r[0-9]]], lsl #8
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; PRE6-NEXT: orr [[R3:r[0-9]+|lr]], [[R2]], [[R0]], lsl #24
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; PRE6-NEXT: lsr [[R4:r[0-9]+|lr]], [[R3]], #16
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; REV-LABEL: bswap16
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;; FIXME: It would ben nice if DAG legalization was taught to not
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;; promote the incoming reg to i32 in this case, so that the
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;; combiner could canonicalize this to (rotr (bswap x), 16), which
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;; would then get matched as REV16.
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; REV: rev [[R0:r[0-9]+|lr]], {{r[0-9]+}}
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; REV-NEXT: lsr {{r[0-9]+}}, [[R0]], #16
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}
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define i32 @bswap32(i32 %x) #0 {
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%1 = tail call i32 @llvm.bswap.i32(i32 %x)
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ret i32 %1
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; PRE6-LABEL: bswap32
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; PRE6-DAG: mov [[R0:r[0-9]+|lr]], #65280
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: and [[R0]], [[R0]], [[R1:r[0-9]+|lr]], lsr #8
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; PRE6-DAG: orr [[R0]], [[R0]], [[R1]], lsr #24
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; PRE6-DAG: mov [[R2:r[0-9]+|lr]], #16711680
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; PRE6-DAG: and [[R2]], [[R2]], [[R1]], lsl #8
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; PRE6-DAG: orr [[R1]], [[R2]], [[R1]], lsl #24
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: orr [[R1]], [[R1]], [[R0]]
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; REV-LABEL: bswap32
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; REV: rev {{r[0-9]+|lr}}, {{r[0-9]+|lr}}
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; REV-NOT: rev
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}
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define i48 @bswap48(i48 %x) #0 {
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%1 = tail call i48 @llvm.bswap.i48(i48 %x)
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ret i48 %1
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; PRE6-LABEL: bswap48
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; PRE6-DAG: mov [[R0:r[0-9]+|lr]], #65280
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; PRE6-DAG: mov [[R1:r[0-9]+|lr]], #16711680
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: and [[R0]], [[R0]], [[R2:r[0-9]+|lr]], lsr #8
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; PRE6-DAG: and [[R3:r[0-9]+|lr]], [[R1]], [[R2]], lsl #8
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; PRE6-DAG: orr [[R0]], [[R0]], [[R2]], lsr #24
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; PRE6-DAG: orr [[R2]], [[R3]], [[R2]], lsl #24
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; PRE6-DAG: orr [[R0]], [[R2]], [[R0]]
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: and [[R2]], [[R1]], [[R4:r[0-9]+|lr]], lsl #8
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; PRE6-DAG: orr [[R2]], [[R2]], [[R4]], lsl #24
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; PRE6-DAG: lsr [[R4]], [[R0]], #16
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; PRE6-DAG: lsr [[R2]], [[R2]], #16
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: orr [[R2]], [[R2]], [[R0]], lsl #16
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; PRE6BE-LABEL: bswap48
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; PRE6BE-DAG: mov [[R0:r[0-9]+|lr]], #65280
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; PRE6BE-DAG: mov [[R1:r[0-9]+|lr]], #16711680
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; PRE6-NOT: DAG-BREAK!
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; PRE6BE-DAG: and [[R0]], [[R0]], [[R2:r[0-9]+|lr]], lsr #8
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; PRE6BE-DAG: and [[R3:r[0-9]+|lr]], [[R1]], [[R2:r[0-9]+|lr]], lsl #8
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; PRE6BE-DAG: orr [[R0]], [[R0]], [[R2]], lsr #24
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; PRE6BE-DAG: orr [[R2]], [[R3]], [[R2]], lsl #24
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; PRE6BE-DAG: orr [[R0]], [[R2]], [[R0]]
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; PRE6-NOT: DAG-BREAK!
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; PRE6BE-DAG: and [[R2]], [[R1]], [[R4:r[0-9]+|lr]], lsl #8
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; PRE6BE-DAG: orr [[R4]], [[R2]], [[R4]], lsl #24
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; PRE6BE-DAG: lsr [[R4]], [[R4]], #16
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; PRE6BE-DAG: lsr [[R4]], [[R0]], #16
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; PRE6-NOT: DAG-BREAK!
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; PRE6BE-DAG: orr [[R2]], [[R4]], [[R0]], lsl #16
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; REV-LABEL: bswap48
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; REV-DAG: rev [[R0:r[0-9]+]], [[R1:r[0-9]+]]
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; REV-DAG: rev [[R1]], [[R2:r[0-9]+]]
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; REV-DAG: lsr [[R1]], [[R1]], #16
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; REV-DAG: lsr [[R2]], [[R0]], #16
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; REV-DAG: orr [[R1]], [[R1]], [[R0]], lsl #16
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; REVBE-LABEL: bswap48
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; Until PR24879 is fixed, I can't match [[R0:r[0-9]+|lr]] in a
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; backreference. Having to stick to just r[0-9]+ for now, which
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; is *very* likely to be the register selection :-).
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; REVBE-DAG: rev [[R0:r[0-9]+]], [[R0]]
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; Need to break DAG block here to stop R1 or R2 clobbering the
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; self rev above.
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; REVBE-NEXT: rev [[R1:r[0-9]+|lr]], [[R2:r[0-9]+|lr]]
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; REVBE-DAG: lsr [[R0]], [[R0]], #16
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; REVBE-DAG: lsr [[R0]], [[R1]], #16
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; REVBE-DAG: orr [[R2]], [[R0]], [[R1]], lsl #16
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}
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define i64 @bswap64(i64 %x) #0 {
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%1 = tail call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %1
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; PRE6-LABEL: bswap64
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; PRE6-DAG: mov [[R0:r[0-9]+|lr]], #65280
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; PRE6-DAG: mov [[R1:r[0-9]+|lr]], #16711680
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: and [[R2:r[0-9]+|lr]], [[R0]], [[R3:r[0-9]+|lr]], lsr #8
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; PRE6-DAG: and [[R4:r[0-9]+|lr]], [[R1]], [[R3]], lsl #8
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; PRE6-DAG: orr [[R2]], [[R2]], [[R3]], lsr #24
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; PRE6: orr [[R3]], [[R4]], [[R3]], lsl #24
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; PRE6-NOT: DAG-BREAK!
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; PRE6-DAG: and [[R4]], [[R1]], [[R5:r[0-9]+|lr]], lsl #8
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; PRE6-DAG: orr [[R2]], [[R3]], [[R2]]
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; PRE6-DAG: and [[R3]], [[R0]], [[R5]], lsr #8
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; PRE6-DAG: orr [[R3]], [[R3]], [[R5]], lsr #24
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; PRE6-DAG: orr [[R5]], [[R4]], [[R5]], lsl #24
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; PRE6-DAG: orr [[R3]], [[R5]], [[R3]]
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; REV-LABEL: bswap64
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; Just check that the two 32-bit words are reversed, not bothered
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; so much about regiter selection here.
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; REV: rev
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; REV: rev
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; REV-NOT: rev
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}
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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declare i48 @llvm.bswap.i48(i48)
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declare i64 @llvm.bswap.i64(i64)
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