forked from OSchip/llvm-project
[PowerPC] Implement hasBitPreservingFPLogic for types that can be supported
This is the PPC-specific non-controversial part of https://reviews.llvm.org/D44548 that simply enables this combine for PPC since PPC has these instructions. This commit will allow the target-independent portion to be truly target independent. llvm-svn: 344077
This commit is contained in:
Nemanja Ivanovic
parent
e3ccd28660
commit
87873d04c3
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@ -14320,6 +14320,15 @@ bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
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return getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), Callee);
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}
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bool PPCTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
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if (!Subtarget.hasVSX())
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return false;
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if (Subtarget.hasP9Vector() && VT == MVT::f128)
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return true;
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return VT == MVT::f32 || VT == MVT::f64 ||
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VT == MVT::v4f32 || VT == MVT::v2f64;
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}
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bool PPCTargetLowering::
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isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
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const Value *Mask = AndI.getOperand(1);
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@ -1127,6 +1127,7 @@ namespace llvm {
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// tail call. This will cause the optimizers to attempt to move, or
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// duplicate return instructions to help enable tail call optimizations.
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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bool hasBitPreservingFPLogic(EVT VT) const override;
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bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
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}; // end class PPCTargetLowering
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@ -0,0 +1,126 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unkknown-unknown \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s
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define float @absf(float %a) {
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; CHECK-LABEL: absf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fabs f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast float %a to i32
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%and = and i32 %conv, 2147483647
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @absd(double %a) {
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; CHECK-LABEL: absd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsabsdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast double %a to i64
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%and = and i64 %conv, 9223372036854775807
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @absv4f32(<4 x float> %a) {
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; CHECK-LABEL: absv4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvabssp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = and <4 x i32> %conv, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <4 x float> @absv4f32_wundef(<4 x float> %a) {
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; CHECK-LABEL: absv4f32_wundef:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvabssp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <4 x float> @absv4f32_invalid(<4 x float> %a) {
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; CHECK-LABEL: absv4f32_invalid:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; CHECK-NEXT: lvx v3, 0, r3
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; CHECK-NEXT: xxland vs34, vs34, vs35
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @absv2f64(<2 x double> %a) {
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; CHECK-LABEL: absv2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvabsdp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = and <2 x i64> %conv, <i64 9223372036854775807, i64 9223372036854775807>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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define float @negf(float %a) {
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; CHECK-LABEL: negf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fneg f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast float %a to i32
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%and = xor i32 %conv, -2147483648
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @negd(double %a) {
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; CHECK-LABEL: negd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsnegdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast double %a to i64
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%and = xor i64 %conv, -9223372036854775808
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @negv4f32(<4 x float> %a) {
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; CHECK-LABEL: negv4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvnegsp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = xor <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @negv2d64(<2 x double> %a) {
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; CHECK-LABEL: negv2d64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvnegdp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = xor <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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