forked from OSchip/llvm-project
[ARM] Add command-line option for SB
SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also renames FeatureSpecRestrict to FeatureSB. Reviewed By: olista01, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55990 llvm-svn: 350299
This commit is contained in:
Diogo N. Sampaio
parent
31d7305258
commit
8786a946d8
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@ -158,6 +158,7 @@ ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, nullptr, nullptr)
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ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr)
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ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
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ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml")
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ARM_ARCH_EXT_NAME("sb", ARM::AEK_SB, "+sb", "-sb")
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#undef ARM_ARCH_EXT_NAME
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#ifndef ARM_HW_DIV_NAME
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@ -45,6 +45,7 @@ enum ArchExtKind : unsigned {
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AEK_SHA2 = 1 << 15,
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AEK_AES = 1 << 16,
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AEK_FP16FML = 1 << 17,
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AEK_SB = 1 << 18,
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// Unsupported extensions.
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AEK_OS = 0x8000000,
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AEK_IWMMXT = 0x10000000,
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@ -365,8 +365,8 @@ def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
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// Armv8.5-A extensions
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def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
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"Enable speculation control barrier" >;
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def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
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"Enable v8.5a Speculation Barrier" >;
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//===----------------------------------------------------------------------===//
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// ARM architecture class
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@ -459,7 +459,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
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def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
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"Support ARM v8.5a instructions",
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[HasV8_4aOps, FeatureSpecCtrl]>;
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[HasV8_4aOps, FeatureSB]>;
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//===----------------------------------------------------------------------===//
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// ARM Processor subtarget features.
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@ -395,8 +395,8 @@ let RecomputePerFunction = 1 in {
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def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
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// Armv8.5-A extensions
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def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
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AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
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def HasSB : Predicate<"Subtarget->hasSB()">,
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AssemblerPredicate<"FeatureSB", "sb">;
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//===----------------------------------------------------------------------===//
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// ARM Flag Definitions.
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@ -4895,7 +4895,7 @@ def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary,
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// Armv8.5-A speculation barrier
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def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>,
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Requires<[IsARM, HasSpecCtrl]>, Sched<[]> {
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Requires<[IsARM, HasSB]>, Sched<[]> {
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let Inst{31-0} = 0xf57ff070;
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let Unpredictable = 0x000fff0f;
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let hasSideEffects = 1;
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@ -3239,7 +3239,7 @@ def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary,
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// Armv8.5-A speculation barrier
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def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
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Requires<[IsThumb2, HasSpecCtrl]>, Sched<[]> {
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Requires<[IsThumb2, HasSB]>, Sched<[]> {
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let Inst{31-0} = 0xf3bf8f70;
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let Unpredictable = 0x000f2f0f;
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let hasSideEffects = 1;
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@ -417,7 +417,7 @@ protected:
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bool UseSjLjEH = false;
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/// Has speculation barrier
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bool HasSpecCtrl = false;
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bool HasSB = false;
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/// Implicitly convert an instruction to a different one if its immediates
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/// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
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@ -628,7 +628,7 @@ public:
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bool hasDSP() const { return HasDSP; }
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bool useNaClTrap() const { return UseNaClTrap; }
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bool useSjLjEH() const { return UseSjLjEH; }
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bool hasSpecCtrl() const { return HasSpecCtrl; }
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bool hasSB() const { return HasSB; }
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bool genLongCalls() const { return GenLongCalls; }
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bool genExecuteOnly() const { return GenExecuteOnly; }
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@ -0,0 +1,6 @@
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// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s 2>&1 | FileCheck %s
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it eq
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sbeq
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// CHECK: instruction 'sb' is not predicable, but condition code specified
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@ -0,0 +1,5 @@
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// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s 2>&1 | FileCheck %s
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sbeq
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// CHECK: instruction 'sb' is not predicable
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@ -0,0 +1,15 @@
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// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s | FileCheck %s
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// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
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// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s | FileCheck %s --check-prefix=THUMB
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// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
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// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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// Flag manipulation
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sb
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// CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
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// THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
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// NOSB: instruction requires: sb
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// NOSB-NEXT: sb
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@ -1,6 +0,0 @@
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// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
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it eq
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sbeq
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// CHECK: instruction 'sb' is not predicable, but condition code specified
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@ -1,5 +0,0 @@
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// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
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sbeq
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// CHECK: instruction 'sb' is not predicable
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@ -1,15 +0,0 @@
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// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s
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// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
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// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s --check-prefix=THUMB
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// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
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// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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// Flag manipulation
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sb
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// CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
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// THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
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// NOSB: instruction requires: specctrl
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// NOSB-NEXT: sb
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@ -0,0 +1,9 @@
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# RUN: llvm-mc -triple=thumbv8 -mattr=+sb -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=thumbv8 -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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0xbf 0xf3 0x70 0x8f
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# CHECK: sb
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# NOSB: invalid instruction encoding
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# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
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@ -1,9 +0,0 @@
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# RUN: llvm-mc -triple=thumbv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=thumbv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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0xbf 0xf3 0x70 0x8f
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# CHECK: sb
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# NOSB: invalid instruction encoding
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# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
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@ -584,7 +584,8 @@ TEST(TargetParserTest, ARMArchExtFeature) {
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{"iwmmxt", "noiwmmxt", nullptr, nullptr},
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{"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
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{"maverick", "maverick", nullptr, nullptr},
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{"xscale", "noxscale", nullptr, nullptr}};
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{"xscale", "noxscale", nullptr, nullptr},
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{"sb", "nosb", "+sb", "-sb"}};
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for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
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EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));
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