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Strength-reduce SmallVectors to arrays. NFCI.

This commit is contained in:
Benjamin Kramer 2020-08-28 21:14:20 +02:00
parent 52cc97a0db
commit 8782c72765
6 changed files with 16 additions and 18 deletions
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4
clang/lib/Driver/ToolChains/AMDGPU.cpp
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@ -245,9 +245,9 @@ void RocmInstallationDetector::detectDeviceLibrary() {
// - ${ROCM_ROOT}/lib/*
// - ${ROCM_ROOT}/lib/bitcode/*
// so try to detect these layouts.
static llvm::SmallVector<const char *, 2> SubDirsList[] = {
static constexpr std::array<const char *, 2> SubDirsList[] = {
{"amdgcn", "bitcode"},
{"lib"},
{"lib", ""},
{"lib", "bitcode"},
};

2
llvm/lib/IR/DebugInfoMetadata.cpp
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@ -133,7 +133,7 @@ const DILocation *DILocation::getMergedLocation(const DILocation *LocA,
}
Optional<unsigned> DILocation::encodeDiscriminator(unsigned BD, unsigned DF, unsigned CI) {
SmallVector<unsigned, 3> Components = {BD, DF, CI};
std::array<unsigned, 3> Components = {BD, DF, CI};
uint64_t RemainingWork = 0U;
// We use RemainingWork to figure out if we have no remaining components to
// encode. For example: if BD != 0 but DF == 0 && CI == 0, we don't need to

4
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -15710,8 +15710,8 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(
auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
EVT CmpVT = Pg.getValueType();
SmallVector<SDValue, 4> CmpOps = {Pg, Op1, Op2, Op.getOperand(2)};
auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT, CmpOps);
auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT,
{Pg, Op1, Op2, Op.getOperand(2)});
EVT PromoteVT = ContainerVT.changeTypeToInteger();
auto Promote = DAG.getBoolExtOrTrunc(Cmp, DL, PromoteVT, InVT);

2
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
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@ -3156,7 +3156,7 @@ static bool mergeConditionalStoreToAddress(BasicBlock *PTB, BasicBlock *PFB,
return true;
};
const SmallVector<StoreInst *, 2> FreeStores = {PStore, QStore};
const std::array<StoreInst *, 2> FreeStores = {PStore, QStore};
if (!MergeCondStoresAggressively &&
(!IsWorthwhile(PTB, FreeStores) || !IsWorthwhile(PFB, FreeStores) ||
!IsWorthwhile(QTB, FreeStores) || !IsWorthwhile(QFB, FreeStores)))

5
mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
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@ -377,11 +377,10 @@ fuseProducerOfDep(OpBuilder &b, LinalgOp consumer, unsigned consumerIdx,
Optional<FusionInfo> mlir::linalg::fuseProducerOf(
OpBuilder &b, LinalgOp consumer, unsigned consumerIdx,
const LinalgDependenceGraph &graph, OperationFolder *folder) {
SmallVector<LinalgDependenceGraph::DependenceType, 4> deps = {
for (auto dep : {
LinalgDependenceGraph::DependenceType::RAW,
LinalgDependenceGraph::DependenceType::WAW,
};
for (auto dep : deps) {
}) {
if (auto res =
fuseProducerOfDep(b, consumer, consumerIdx, graph, folder, dep))
return res;

13
mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
View File

@ -2849,9 +2849,9 @@ static ParseResult parseCooperativeMatrixLoadNVOp(OpAsmParser &parser,
parser.parseType(ptrType) || parser.parseKeywordType("as", elementType)) {
return failure();
}
SmallVector<Type, 3> OperandType = {ptrType, strideType, columnMajorType};
if (parser.resolveOperands(operandInfo, OperandType, parser.getNameLoc(),
state.operands)) {
if (parser.resolveOperands(operandInfo,
{ptrType, strideType, columnMajorType},
parser.getNameLoc(), state.operands)) {
return failure();
}
@ -2904,10 +2904,9 @@ static ParseResult parseCooperativeMatrixStoreNVOp(OpAsmParser &parser,
parser.parseType(elementType)) {
return failure();
}
SmallVector<Type, 4> OperandType = {ptrType, elementType, strideType,
columnMajorType};
if (parser.resolveOperands(operandInfo, OperandType, parser.getNameLoc(),
state.operands)) {
if (parser.resolveOperands(
operandInfo, {ptrType, elementType, strideType, columnMajorType},
parser.getNameLoc(), state.operands)) {
return failure();
}