forked from OSchip/llvm-project
parent
6c35893aa6
commit
87585d72a5
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@ -300,7 +300,7 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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"Not expecting virtual register!");
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if (!MO.isDef()) {
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if (PhysRegDefs[Reg])
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if (Reg && PhysRegDefs[Reg])
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// If it's using a non-loop-invariant register, then it's obviously not
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// safe to hoist.
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HasNonInvariantUse = true;
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@ -406,7 +406,7 @@ void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
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MachineInstr *MI = Candidates[i].MI;
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for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg() || MO.isDef())
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if (!MO.isReg() || MO.isDef() || !MO.getReg())
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continue;
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if (PhysRegDefs[MO.getReg()]) {
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// If it's using a non-loop-invariant register, then it's obviously
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@ -502,6 +502,9 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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/// candidate for LICM. e.g. If the instruction is a call, then it's obviously
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/// not safe to hoist it.
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bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
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if (I.isImplicitDef())
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return false;
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const TargetInstrDesc &TID = I.getDesc();
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// Ignore stuff that we obviously can't hoist.
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@ -620,9 +623,6 @@ bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
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/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
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/// the given loop invariant.
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bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
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if (MI.isImplicitDef())
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return false;
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// FIXME: For now, only hoist re-materilizable instructions. LICM will
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// increase register pressure. We want to make sure it doesn't increase
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// spilling.
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