diff --git a/llvm/test/CodeGen/ARM/rev.ll b/llvm/test/CodeGen/ARM/rev.ll
index b97dbc844e00..d7875af04e9c 100644
--- a/llvm/test/CodeGen/ARM/rev.ll
+++ b/llvm/test/CodeGen/ARM/rev.ll
@@ -1,22 +1,24 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-ARM
+; RUN: llc -mtriple=thumbv6m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V6
+; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V7
 
 define i32 @test1(i32 %X) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    rev16 r0, r0
 ; CHECK-NEXT:    bx lr
-        %tmp1 = lshr i32 %X, 8
-        %X15 = bitcast i32 %X to i32
-        %tmp4 = shl i32 %X15, 8
-        %tmp2 = and i32 %tmp1, 16711680
-        %tmp5 = and i32 %tmp4, -16777216
-        %tmp9 = and i32 %tmp1, 255
-        %tmp13 = and i32 %tmp4, 65280
-        %tmp6 = or i32 %tmp5, %tmp2
-        %tmp10 = or i32 %tmp6, %tmp13
-        %tmp14 = or i32 %tmp10, %tmp9
-        ret i32 %tmp14
+  %tmp1 = lshr i32 %X, 8
+  %X15 = bitcast i32 %X to i32
+  %tmp4 = shl i32 %X15, 8
+  %tmp2 = and i32 %tmp1, 16711680
+  %tmp5 = and i32 %tmp4, -16777216
+  %tmp9 = and i32 %tmp1, 255
+  %tmp13 = and i32 %tmp4, 65280
+  %tmp6 = or i32 %tmp5, %tmp2
+  %tmp10 = or i32 %tmp6, %tmp13
+  %tmp14 = or i32 %tmp10, %tmp9
+  ret i32 %tmp14
 }
 
 define i32 @test2(i32 %X) nounwind {
@@ -24,14 +26,14 @@ define i32 @test2(i32 %X) nounwind {
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    revsh r0, r0
 ; CHECK-NEXT:    bx lr
-        %tmp1 = lshr i32 %X, 8
-        %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
-        %tmp3 = trunc i32 %X to i16
-        %tmp2 = and i16 %tmp1.upgrd.1, 255
-        %tmp4 = shl i16 %tmp3, 8
-        %tmp5 = or i16 %tmp2, %tmp4
-        %tmp5.upgrd.2 = sext i16 %tmp5 to i32
-        ret i32 %tmp5.upgrd.2
+  %tmp1 = lshr i32 %X, 8
+  %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
+  %tmp3 = trunc i32 %X to i16
+  %tmp2 = and i16 %tmp1.upgrd.1, 255
+  %tmp4 = shl i16 %tmp3, 8
+  %tmp5 = or i16 %tmp2, %tmp4
+  %tmp5.upgrd.2 = sext i16 %tmp5 to i32
+  ret i32 %tmp5.upgrd.2
 }
 
 ; rdar://9147637
@@ -66,10 +68,24 @@ entry:
 
 ; rdar://9609059
 define i32 @test5(i32 %i) nounwind readnone {
-; CHECK-LABEL: test5:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    revsh r0, r0
-; CHECK-NEXT:    bx lr
+; CHECK-ARM-LABEL: test5:
+; CHECK-ARM:       @ %bb.0: @ %entry
+; CHECK-ARM-NEXT:    revsh r0, r0
+; CHECK-ARM-NEXT:    bx lr
+;
+; CHECK-V6-LABEL: test5:
+; CHECK-V6:       @ %bb.0: @ %entry
+; CHECK-V6-NEXT:    lsrs r1, r0, #8
+; CHECK-V6-NEXT:    uxtb r1, r1
+; CHECK-V6-NEXT:    lsls r0, r0, #24
+; CHECK-V6-NEXT:    asrs r0, r0, #16
+; CHECK-V6-NEXT:    adds r0, r0, r1
+; CHECK-V6-NEXT:    bx lr
+;
+; CHECK-V7-LABEL: test5:
+; CHECK-V7:       @ %bb.0: @ %entry
+; CHECK-V7-NEXT:    revsh r0, r0
+; CHECK-V7-NEXT:    bx lr
 entry:
   %shl = shl i32 %i, 24
   %shr = ashr exact i32 %shl, 16
@@ -100,11 +116,23 @@ entry:
 
 ; rdar://9164521
 define i32 @test7(i32 %a) nounwind readnone {
-; CHECK-LABEL: test7:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    rev r0, r0
-; CHECK-NEXT:    lsr r0, r0, #16
-; CHECK-NEXT:    bx lr
+; CHECK-ARM-LABEL: test7:
+; CHECK-ARM:       @ %bb.0: @ %entry
+; CHECK-ARM-NEXT:    rev r0, r0
+; CHECK-ARM-NEXT:    lsr r0, r0, #16
+; CHECK-ARM-NEXT:    bx lr
+;
+; CHECK-V6-LABEL: test7:
+; CHECK-V6:       @ %bb.0: @ %entry
+; CHECK-V6-NEXT:    rev r0, r0
+; CHECK-V6-NEXT:    lsrs r0, r0, #16
+; CHECK-V6-NEXT:    bx lr
+;
+; CHECK-V7-LABEL: test7:
+; CHECK-V7:       @ %bb.0: @ %entry
+; CHECK-V7-NEXT:    rev r0, r0
+; CHECK-V7-NEXT:    lsrs r0, r0, #16
+; CHECK-V7-NEXT:    bx lr
 entry:
   %and = lshr i32 %a, 8
   %shr3 = and i32 %and, 255
@@ -143,3 +171,13 @@ entry:
   %conv3 = trunc i32 %or to i16
   ret i16 %conv3
 }
+
+define zeroext i16 @test10(i16 zeroext %v) nounwind readnone {
+; CHECK-LABEL: test10:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    rev16 r0, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %conv3 = call i16 @llvm.bswap.i16(i16 %v)
+  ret i16 %conv3
+}