forked from OSchip/llvm-project
[mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction
Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
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@ -64,6 +64,7 @@ private:
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return false;
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case Mips::JAL:
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case Mips::BAL:
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case Mips::BAL_BR:
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case Mips::BLTZAL:
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case Mips::BGEZAL:
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@ -64,6 +64,7 @@ def OPCODE5_BC1EQZ : OPCODE5<0b01001>;
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def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
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def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
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def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
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def OPCODE5_BGEZAL : OPCODE5<0b10001>;
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class OPCODE6<bits<6> Val> {
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bits<6> Value = Val;
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@ -145,6 +146,17 @@ class DAUI_FM : AUI_FM {
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let Inst{31-26} = OPGROUP_DAUI.Value;
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}
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class BAL_FM : MipsR6Inst {
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_REGIMM.Value;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = OPCODE5_BGEZAL.Value;
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let Inst{15-0} = offset;
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}
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class COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
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bits<5> fs;
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bits<5> fd;
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@ -26,8 +26,6 @@ include "Mips32r6InstrFormats.td"
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// Reencoded: sdc2
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// Reencoded: swc2
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// Removed: bc1any2, bc1any4
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// Removed: bgezal
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// Removed: bltzal
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// Rencoded: [ls][wd]c2
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def brtarget21 : Operand<OtherVT> {
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@ -66,6 +64,7 @@ class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
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class AUI_ENC : AUI_FM;
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class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
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class BAL_ENC : BAL_FM;
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class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
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class BC_ENC : BRANCH_OFF26_FM<0b110010>;
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class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
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@ -309,6 +308,12 @@ class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
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list<Register> Defs = [AT];
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}
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class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
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bit isCall = 1;
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bit hasDelaySlot = 1;
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list<Register> Defs = [RA];
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}
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class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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@ -535,6 +540,7 @@ def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
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def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
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def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
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def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
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def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
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def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
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def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
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def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
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@ -1188,8 +1188,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
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// FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
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def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
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def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
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def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
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def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
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def TAILCALL : TailCall<J>;
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def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
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@ -1366,7 +1368,8 @@ def : MipsInstAlias<"move $dst, $src",
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GPR_32 {
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let AdditionalPredicates = [NotInMicroMips];
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}
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def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
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def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"addu $rs, $rt, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : MipsInstAlias<"add $rs, $rt, $imm",
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@ -266,6 +266,13 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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LongBrMBB->addSuccessor(BalTgtMBB);
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BalTgtMBB->addSuccessor(TgtMBB);
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// We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal
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// instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
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// pseudo-instruction wrapping BGEZAL).
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const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
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if (ABI != MipsSubtarget::N64) {
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// $longbr:
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// addiu $sp, $sp, -8
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@ -307,9 +314,11 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
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.addMBB(TgtMBB).addMBB(BalTgtMBB);
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
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.addReg(Mips::AT).addMBB(TgtMBB).addMBB(BalTgtMBB));
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.append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
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.addReg(Mips::AT)
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.addMBB(TgtMBB)
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.addMBB(BalTgtMBB));
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Pos = BalTgtMBB->begin();
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@ -379,11 +388,12 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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.addReg(Mips::AT_64).addImm(16);
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
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Mips::AT_64).addReg(Mips::AT_64)
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.addMBB(TgtMBB, MipsII::MO_ABS_LO)
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.addMBB(BalTgtMBB));
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.append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
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.append(
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BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64)
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.addMBB(TgtMBB, MipsII::MO_ABS_LO)
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.addMBB(BalTgtMBB));
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Pos = BalTgtMBB->begin();
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@ -15,6 +15,10 @@
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bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -15,6 +15,10 @@
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bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -15,6 +15,10 @@
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bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -17,6 +17,10 @@
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -17,6 +17,10 @@
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -19,6 +19,7 @@
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aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
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aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
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auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
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bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8]
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bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01]
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@ -17,6 +17,10 @@
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -17,6 +17,10 @@
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -17,6 +17,10 @@
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bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
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bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
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bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
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bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
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bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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@ -6,6 +6,9 @@
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.set noat
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addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@ -6,6 +6,9 @@
|
|||
|
||||
.set noat
|
||||
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
|
|
@ -6,6 +6,9 @@
|
|||
|
||||
.set noat
|
||||
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
|
|
@ -5,6 +5,9 @@
|
|||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
|
|
@ -5,5 +5,8 @@
|
|||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
|
|
@ -6,6 +6,9 @@
|
|||
|
||||
.set noat
|
||||
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dadd $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
|
||||
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
|
||||
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
|
||||
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
|
||||
balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
|
||||
bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8]
|
||||
bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01]
|
||||
|
|
Loading…
Reference in New Issue