forked from OSchip/llvm-project
Refactor operand adding out to a new AddOperand method
llvm-svn: 26358
This commit is contained in:
Chris Lattner
parent
bbc861543f
commit
86c51000db
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@ -110,6 +110,85 @@ static unsigned CreateVirtualRegisters(MachineInstr *MI,
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return ResultReg;
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
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unsigned IIOpNum,
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const TargetInstrDescriptor *II) {
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if (Op.isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op);
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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assert(II->OpInfo[IIOpNum].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op)) {
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =
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dyn_cast<RegisterSDNode>(Op)) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Op)) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Op)) {
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MI->addFrameIndexOperand(FI->getIndex());
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Op)) {
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unsigned Align = CP->getAlignment();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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if (CP->get()->getType() == Type::DoubleTy)
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Align = 3; // always 8-byte align doubles.
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else
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Align = TM.getTargetData()
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.getTypeAlignmentShift(CP->get()->getType());
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}
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unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
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MI->addConstantPoolIndexOperand(Idx);
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Op)) {
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MI->addExternalSymbolOperand(ES->getSymbol(), false);
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} else {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = getVR(Op);
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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assert(II->OpInfo[IIOpNum].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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}
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}
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/// EmitNode - Generate machine code for an node and needed dependencies.
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///
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void ScheduleDAG::EmitNode(NodeInfo *NI) {
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@ -159,72 +238,8 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0; i != NodeOperands; ++i) {
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if (Node->getOperand(i).isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Node->getOperand(i).getValueType() != MVT::Other &&
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Node->getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Node->getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =
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dyn_cast<RegisterSDNode>(Node->getOperand(i))) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
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MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Node->getOperand(i))) {
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MI->addFrameIndexOperand(FI->getIndex());
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Node->getOperand(i))) {
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unsigned Align = CP->getAlignment();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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if (CP->get()->getType() == Type::DoubleTy)
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Align = 3; // always 8-byte align doubles.
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else
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Align = TM.getTargetData()
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.getTypeAlignmentShift(CP->get()->getType());
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}
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unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
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MI->addConstantPoolIndexOperand(Idx);
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Node->getOperand(i))) {
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MI->addExternalSymbolOperand(ES->getSymbol(), false);
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} else {
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assert(Node->getOperand(i).getValueType() != MVT::Other &&
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Node->getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = getVR(Node->getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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}
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for (unsigned i = 0; i != NodeOperands; ++i)
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AddOperand(MI, Node->getOperand(i), i+NumResults, &II);
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// Now that we have emitted all operands, emit this instruction itself.
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if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
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