forked from OSchip/llvm-project
[AMDGPU] added SIInstrInfo::getAddNoCarry() helper
Addressed rest of post submit comments from D31993. Differential Revision: https://reviews.llvm.org/D32057 llvm-svn: 300288
This commit is contained in:
Stanislav Mekhanoshin
parent
8f56846d4f
commit
86b0a5465b
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@ -3930,3 +3930,16 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {
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return !MI.isTerminator() && MI.getOpcode() != AMDGPU::COPY &&
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MI.modifiesRegister(AMDGPU::EXEC, &RI);
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}
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MachineInstrBuilder
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SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL,
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unsigned DestReg) const {
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
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.addReg(UnusedCarry, RegState::Define | RegState::Dead);
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}
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@ -761,6 +761,15 @@ public:
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CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
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bool isBasicBlockPrologue(const MachineInstr &MI) const override;
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/// \brief Return a partially built integer add instruction without carry.
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/// Caller must add source operands.
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/// For pre-GFX9 it will generate unused carry destination operand.
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/// TODO: After GFX9 it should return a no-carry operation.
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MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL,
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unsigned DestReg) const;
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};
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namespace AMDGPU {
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@ -389,13 +389,14 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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.addReg(AddrReg->getReg());
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}
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MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
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MachineInstrBuilder Read2 =
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BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
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.addReg(BaseReg, BaseRegFlags) // addr
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset1) // offset1
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.addImm(0) // gds
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.addMemOperand(*CI.I->memoperands_begin())
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.addMemOperand(*CI.Paired->memoperands_begin());
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.setMemRefs(CI.I->mergeMemRefsWith(*CI.Paired));
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(void)Read2;
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const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
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@ -461,15 +462,15 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
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.addReg(Addr->getReg());
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}
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MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc)
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MachineInstrBuilder Write2 =
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BuildMI(*MBB, CI.Paired, DL, Write2Desc)
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.addReg(BaseReg, BaseRegFlags) // addr
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.add(*Data0) // data0
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.add(*Data1) // data1
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset1) // offset1
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.addImm(0) // gds
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.addMemOperand(*CI.I->memoperands_begin())
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.addMemOperand(*CI.Paired->memoperands_begin());
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.setMemRefs(CI.I->mergeMemRefsWith(*CI.Paired));
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moveInstsAfter(Write2, CI.InstsToMove);
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@ -278,7 +278,6 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
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}
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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unsigned FIReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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@ -288,8 +287,7 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
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BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg)
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.addFrameIndex(FrameIdx);
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BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_ADD_I32_e64), BaseReg)
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.addReg(UnusedCarry, RegState::Define | RegState::Dead)
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TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
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.addReg(OffsetReg, RegState::Kill)
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.addReg(FIReg);
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}
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@ -1,16 +1,20 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
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; CHECK-LABEL: ds_read32_combine_stride_400:
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; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
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define void @ds_read32_combine_stride_400(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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; GCN-LABEL: ds_read32_combine_stride_400:
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; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
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define amdgpu_kernel void @ds_read32_combine_stride_400(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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bb:
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%tmp = load float, float addrspace(3)* %arg, align 4
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%tmp2 = fadd float %tmp, 0.000000e+00
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@ -39,17 +43,20 @@ bb:
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ret void
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}
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; CHECK-LABEL: ds_read32_combine_stride_400_back:
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; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
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; CHECK-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
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define void @ds_read32_combine_stride_400_back(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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; GCN-LABEL: ds_read32_combine_stride_400_back:
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; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
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; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
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define amdgpu_kernel void @ds_read32_combine_stride_400_back(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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bb:
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%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
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%tmp2 = load float, float addrspace(3)* %tmp, align 4
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@ -78,14 +85,14 @@ bb:
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ret void
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}
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; CHECK-LABEL: ds_read32_combine_stride_8192:
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; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:32
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224
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define void @ds_read32_combine_stride_8192(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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; GCN-LABEL: ds_read32_combine_stride_8192:
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; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:32
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224
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define amdgpu_kernel void @ds_read32_combine_stride_8192(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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bb:
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%tmp = load float, float addrspace(3)* %arg, align 4
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%tmp2 = fadd float %tmp, 0.000000e+00
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@ -114,16 +121,19 @@ bb:
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ret void
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}
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; CHECK-LABEL: ds_read32_combine_stride_8192_shifted:
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; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:32
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; CHECK-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:32
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define void @ds_read32_combine_stride_8192_shifted(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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; GCN-LABEL: ds_read32_combine_stride_8192_shifted:
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; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:32
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; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:32
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define amdgpu_kernel void @ds_read32_combine_stride_8192_shifted(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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bb:
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%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
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%tmp2 = load float, float addrspace(3)* %tmp, align 4
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@ -147,15 +157,16 @@ bb:
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ret void
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}
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; CHECK-LABEL: ds_read64_combine_stride_400:
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; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]]
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; CHECK-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
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; CHECK-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150
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; CHECK-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250
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; CHECK-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:50
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define void @ds_read64_combine_stride_400(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
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; GCN-LABEL: ds_read64_combine_stride_400:
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; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]]
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; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]]
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; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
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; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150
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; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250
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; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:50
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define amdgpu_kernel void @ds_read64_combine_stride_400(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
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bb:
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%tmp = load double, double addrspace(3)* %arg, align 8
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%tmp2 = fadd double %tmp, 0.000000e+00
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@ -184,16 +195,19 @@ bb:
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ret void
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}
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; CHECK-LABEL: ds_read64_combine_stride_8192_shifted:
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; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
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; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
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; CHECK-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
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; CHECK-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:16
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; CHECK-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:16
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define void @ds_read64_combine_stride_8192_shifted(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
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; GCN-LABEL: ds_read64_combine_stride_8192_shifted:
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; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
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; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
|
||||
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
|
||||
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:16
|
||||
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:16
|
||||
define amdgpu_kernel void @ds_read64_combine_stride_8192_shifted(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
|
||||
bb:
|
||||
%tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
|
||||
%tmp2 = load double, double addrspace(3)* %tmp, align 8
|
||||
|
|
@ -217,17 +231,20 @@ bb:
|
|||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ds_write32_combine_stride_400:
|
||||
; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; CHECK-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; CHECK-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; CHECK-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; CHECK-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
define void @ds_write32_combine_stride_400(float addrspace(3)* nocapture %arg) {
|
||||
; GCN-LABEL: ds_write32_combine_stride_400:
|
||||
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
define amdgpu_kernel void @ds_write32_combine_stride_400(float addrspace(3)* nocapture %arg) {
|
||||
bb:
|
||||
store float 1.000000e+00, float addrspace(3)* %arg, align 4
|
||||
%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
|
||||
|
|
@ -247,17 +264,20 @@ bb:
|
|||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ds_write32_combine_stride_400_back:
|
||||
; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; CHECK-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; CHECK-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; CHECK-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; CHECK-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
define void @ds_write32_combine_stride_400_back(float addrspace(3)* nocapture %arg) {
|
||||
; GCN-LABEL: ds_write32_combine_stride_400_back:
|
||||
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
|
||||
define amdgpu_kernel void @ds_write32_combine_stride_400_back(float addrspace(3)* nocapture %arg) {
|
||||
bb:
|
||||
%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
|
||||
store float 1.000000e+00, float addrspace(3)* %tmp, align 4
|
||||
|
|
@ -277,14 +297,14 @@ bb:
|
|||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ds_write32_combine_stride_8192:
|
||||
; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; CHECK-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
; CHECK-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96
|
||||
; CHECK-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160
|
||||
; CHECK-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:192 offset1:224
|
||||
define void @ds_write32_combine_stride_8192(float addrspace(3)* nocapture %arg) {
|
||||
; GCN-LABEL: ds_write32_combine_stride_8192:
|
||||
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96
|
||||
; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160
|
||||
; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:192 offset1:224
|
||||
define amdgpu_kernel void @ds_write32_combine_stride_8192(float addrspace(3)* nocapture %arg) {
|
||||
bb:
|
||||
store float 1.000000e+00, float addrspace(3)* %arg, align 4
|
||||
%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2048
|
||||
|
|
@ -304,16 +324,19 @@ bb:
|
|||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ds_write32_combine_stride_8192_shifted:
|
||||
; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4004, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8004, [[BASE]]
|
||||
; CHECK-DAG: ds_write2st64_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
; CHECK-DAG: ds_write2st64_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
; CHECK-DAG: ds_write2st64_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
define void @ds_write32_combine_stride_8192_shifted(float addrspace(3)* nocapture %arg) {
|
||||
; GCN-LABEL: ds_write32_combine_stride_8192_shifted:
|
||||
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4004, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8004, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4004, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8004, [[BASE]]
|
||||
; GCN-DAG: ds_write2st64_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
; GCN-DAG: ds_write2st64_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
; GCN-DAG: ds_write2st64_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
|
||||
define amdgpu_kernel void @ds_write32_combine_stride_8192_shifted(float addrspace(3)* nocapture %arg) {
|
||||
bb:
|
||||
%tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 1
|
||||
store float 1.000000e+00, float addrspace(3)* %tmp, align 4
|
||||
|
|
@ -330,15 +353,16 @@ bb:
|
|||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ds_write64_combine_stride_400:
|
||||
; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; CHECK-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
|
||||
; CHECK-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:100 offset1:150
|
||||
; CHECK-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:200 offset1:250
|
||||
; CHECK-DAG: ds_write2_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
|
||||
define void @ds_write64_combine_stride_400(double addrspace(3)* nocapture %arg) {
|
||||
; GCN-LABEL: ds_write64_combine_stride_400:
|
||||
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]]
|
||||
; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
|
||||
; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:100 offset1:150
|
||||
; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:200 offset1:250
|
||||
; GCN-DAG: ds_write2_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
|
||||
define amdgpu_kernel void @ds_write64_combine_stride_400(double addrspace(3)* nocapture %arg) {
|
||||
bb:
|
||||
store double 1.000000e+00, double addrspace(3)* %arg, align 8
|
||||
%tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 50
|
||||
|
|
@ -358,16 +382,19 @@ bb:
|
|||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ds_write64_combine_stride_8192_shifted:
|
||||
; CHECK: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; CHECK: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
|
||||
; CHECK-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
|
||||
; CHECK-DAG: ds_write2st64_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
||||
; CHECK-DAG: ds_write2st64_b64 [[B2]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
||||
; CHECK-DAG: ds_write2st64_b64 [[B3]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
||||
define void @ds_write64_combine_stride_8192_shifted(double addrspace(3)* nocapture %arg) {
|
||||
; GCN-LABEL: ds_write64_combine_stride_8192_shifted:
|
||||
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
||||
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
|
||||
; GCN-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]]
|
||||
; GFX9-DAG: v_add_i32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]]
|
||||
; GCN-DAG: ds_write2st64_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
||||
; GCN-DAG: ds_write2st64_b64 [[B2]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
||||
; GCN-DAG: ds_write2st64_b64 [[B3]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
||||
define amdgpu_kernel void @ds_write64_combine_stride_8192_shifted(double addrspace(3)* nocapture %arg) {
|
||||
bb:
|
||||
%tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
|
||||
store double 1.000000e+00, double addrspace(3)* %tmp, align 8
|
||||
|
|
|
|||
Loading…
Reference in New Issue