forked from OSchip/llvm-project
Revert "[GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _)" (and dependent patch "Optimize away a Not feeding a brcond by using tbz instead of tbnz.")
This reverts commit8ad8f484b6. It causes crashes when running `ninja check-llvm-codegen-aarch64-globalisel`, e.g. http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/24132/steps/test-stage1-compiler/logs/stdio. Note that the crash does not seem to reproduce in debug builds.5ded444252depends on this, so revert that too.
This commit is contained in:
Jordan Rupprecht
parent
1f4e7463b5
commit
8693ddc743
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@ -355,10 +355,6 @@ public:
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/// \return true if \p MI is a G_SEXT_INREG that can be erased.
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bool matchRedundantSExtInReg(MachineInstr &MI);
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/// Combine inverting a result of a compare into the opposite cond code.
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bool matchNotCmp(MachineInstr &MI, Register &CmpReg);
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bool applyNotCmp(MachineInstr &MI, Register &CmpReg);
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/// Try to transform \p MI by using all of the above
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/// combine functions. Returns true if changed.
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bool tryCombine(MachineInstr &MI);
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@ -233,12 +233,6 @@ m_GAnd(const LHS &L, const RHS &R) {
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return BinaryOp_match<LHS, RHS, TargetOpcode::G_AND, true>(L, R);
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}
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template <typename LHS, typename RHS>
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inline BinaryOp_match<LHS, RHS, TargetOpcode::G_XOR, true>
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m_GXor(const LHS &L, const RHS &R) {
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return BinaryOp_match<LHS, RHS, TargetOpcode::G_XOR, true>(L, R);
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}
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template <typename LHS, typename RHS>
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inline BinaryOp_match<LHS, RHS, TargetOpcode::G_OR, true> m_GOr(const LHS &L,
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const RHS &R) {
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@ -16,7 +16,6 @@
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/Support/Alignment.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include "llvm/Support/MachineValueType.h"
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@ -228,10 +227,6 @@ LLT getGCDType(LLT OrigTy, LLT TargetTy);
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/// If \p MI is not a splat, returns None.
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Optional<int> getSplatIndex(MachineInstr &MI);
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/// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
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Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
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const MachineRegisterInfo &MRI);
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/// Return true if the specified instruction is a G_BUILD_VECTOR or
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/// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
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bool isBuildVectorAllZeros(const MachineInstr &MI,
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@ -242,9 +237,5 @@ bool isBuildVectorAllZeros(const MachineInstr &MI,
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bool isBuildVectorAllOnes(const MachineInstr &MI,
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const MachineRegisterInfo &MRI);
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/// Returns true if given the TargetLowering's boolean contents information,
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/// the value \p Val contains a true value.
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bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
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bool IsFP);
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} // End namespace llvm.
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#endif
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@ -373,14 +373,6 @@ def ext_ext_fold: GICombineRule <
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(apply [{ return Helper.applyCombineExtOfExt(*${root}, ${matchinfo}); }])
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>;
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def not_cmp_fold_matchinfo : GIDefMatchData<"Register">;
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def not_cmp_fold : GICombineRule<
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(defs root:$d, not_cmp_fold_matchinfo:$info),
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(match (wip_match_opcode G_XOR): $d,
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[{ return Helper.matchNotCmp(*${d}, ${info}); }]),
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(apply [{ return Helper.applyNotCmp(*${d}, ${info}); }])
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>;
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// FIXME: These should use the custom predicate feature once it lands.
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def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
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undef_to_negative_one,
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@ -408,5 +400,4 @@ def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain,
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hoist_logic_op_with_same_opcode_hands,
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shl_ashr_to_sext_inreg, sext_inreg_of_load,
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width_reduction_combines, select_combines,
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known_bits_simplifications, ext_ext_fold,
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not_cmp_fold]>;
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known_bits_simplifications, ext_ext_fold]>;
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@ -2231,74 +2231,6 @@ bool CombinerHelper::matchRedundantSExtInReg(MachineInstr &MI) {
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return KB->computeNumSignBits(Src) >= (TypeSize - ExtBits + 1);
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}
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static bool isConstValidTrue(const TargetLowering &TLI, unsigned ScalarSizeBits,
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int64_t Cst, bool IsVector, bool IsFP) {
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// For i1, Cst will always be -1 regardless of boolean contents.
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return (ScalarSizeBits == 1 && Cst == -1) ||
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isConstTrueVal(TLI, Cst, IsVector, IsFP);
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}
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bool CombinerHelper::matchNotCmp(MachineInstr &MI, Register &CmpReg) {
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assert(MI.getOpcode() == TargetOpcode::G_XOR);
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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const auto &TLI = *Builder.getMF().getSubtarget().getTargetLowering();
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Register XorSrc;
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Register CstReg;
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int64_t Cst;
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// We match xor(src, true) here.
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if (!mi_match(MI.getOperand(0).getReg(), MRI,
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m_GXor(m_Reg(XorSrc), m_Reg(CstReg))))
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return false;
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if (!MRI.hasOneNonDBGUse(XorSrc))
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return false;
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// Now try match src to either icmp or fcmp.
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bool IsFP = false;
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if (!mi_match(XorSrc, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()))) {
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// Try fcmp.
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if (!mi_match(XorSrc, MRI, m_GFCmp(m_Pred(), m_Reg(), m_Reg())))
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return false;
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IsFP = true;
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}
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if (Ty.isVector()) {
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MachineInstr *CstDef = MRI.getVRegDef(CstReg);
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auto MaybeCst = getBuildVectorConstantSplat(*CstDef, MRI);
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if (!MaybeCst)
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return false;
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if (!isConstValidTrue(TLI, Ty.getScalarSizeInBits(), *MaybeCst, true, IsFP))
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return false;
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} else {
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if (!mi_match(CstReg, MRI, m_ICst(Cst)))
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return false;
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if (!isConstValidTrue(TLI, Ty.getSizeInBits(), Cst, false, IsFP))
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return false;
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}
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CmpReg = XorSrc;
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return true;
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}
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bool CombinerHelper::applyNotCmp(MachineInstr &MI, Register &CmpReg) {
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MachineInstr *CmpDef = MRI.getVRegDef(CmpReg);
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assert(CmpDef && "Should have been given an MI reg");
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assert(CmpDef->getOpcode() == TargetOpcode::G_ICMP ||
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CmpDef->getOpcode() == TargetOpcode::G_FCMP);
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Observer.changingInstr(*CmpDef);
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MachineOperand &PredOp = CmpDef->getOperand(1);
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CmpInst::Predicate NewP = CmpInst::getInversePredicate(
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(CmpInst::Predicate)PredOp.getPredicate());
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PredOp.setPredicate(NewP);
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Observer.changedInstr(*CmpDef);
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replaceRegWith(MRI, MI.getOperand(0).getReg(),
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CmpDef->getOperand(0).getReg());
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MI.eraseFromParent();
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return true;
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}
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bool CombinerHelper::tryCombine(MachineInstr &MI) {
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if (tryCombineCopy(MI))
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return true;
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@ -11,8 +11,6 @@
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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@ -696,28 +694,6 @@ static bool isBuildVectorConstantSplat(const MachineInstr &MI,
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return true;
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}
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Optional<int64_t>
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llvm::getBuildVectorConstantSplat(const MachineInstr &MI,
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const MachineRegisterInfo &MRI) {
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if (!isBuildVectorOp(MI.getOpcode()))
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return None;
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const unsigned NumOps = MI.getNumOperands();
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Optional<int64_t> Scalar;
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for (unsigned I = 1; I != NumOps; ++I) {
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Register Element = MI.getOperand(I).getReg();
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int64_t ElementValue;
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if (!mi_match(Element, MRI, m_ICst(ElementValue)))
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return None;
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if (!Scalar)
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Scalar = ElementValue;
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else if (*Scalar != ElementValue)
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return None;
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}
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return Scalar;
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}
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bool llvm::isBuildVectorAllZeros(const MachineInstr &MI,
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const MachineRegisterInfo &MRI) {
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return isBuildVectorConstantSplat(MI, MRI, 0);
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@ -727,16 +703,3 @@ bool llvm::isBuildVectorAllOnes(const MachineInstr &MI,
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const MachineRegisterInfo &MRI) {
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return isBuildVectorConstantSplat(MI, MRI, -1);
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}
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bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
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bool IsFP) {
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switch (TLI.getBooleanContents(IsVector, IsFP)) {
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case TargetLowering::UndefinedBooleanContent:
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return Val & 0x1;
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case TargetLowering::ZeroOrOneBooleanContent:
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return Val == 1;
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case TargetLowering::ZeroOrNegativeOneBooleanContent:
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return Val == -1;
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}
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llvm_unreachable("Invalid boolean contents");
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}
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@ -41,7 +41,6 @@
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#define DEBUG_TYPE "aarch64-isel"
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using namespace llvm;
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using namespace MIPatternMatch;
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namespace {
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@ -1884,7 +1883,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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return false;
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}
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Register CondReg = I.getOperand(0).getReg();
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const Register CondReg = I.getOperand(0).getReg();
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MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
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// Speculation tracking/SLH assumes that optimized TB(N)Z/CB(N)Z
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@ -1894,19 +1893,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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return true;
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if (ProduceNonFlagSettingCondBr) {
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unsigned BOpc = AArch64::TBNZW;
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// Try to fold a not, i.e. a xor, cond, 1.
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Register XorSrc;
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int64_t Cst;
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if (mi_match(CondReg, MRI,
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m_GTrunc(m_GXor(m_Reg(XorSrc), m_ICst(Cst)))) &&
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Cst == 1) {
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CondReg = XorSrc;
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BOpc = AArch64::TBZW;
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if (MRI.getType(XorSrc).getSizeInBits() > 32)
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BOpc = AArch64::TBZX;
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}
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auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(BOpc))
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auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
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.addUse(CondReg)
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.addImm(/*bit offset=*/0)
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.addMBB(DestMBB);
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@ -1,163 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombinerhelper-only-enable-rule="not_cmp_fold" %s -o - -verify-machineinstrs | FileCheck %s
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# Check that we fold an compare result inverted into just inverting the condition code.
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---
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name: icmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: fcmp
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: fcmp
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](s64), [[C]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 1
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%3:_(s1) = G_FCMP floatpred(ogt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_not_xor_with_1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_not_xor_with_1
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s1) = G_CONSTANT i1 0
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%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s1) = G_XOR %3, %2
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%5:_(s32) = G_ANYEXT %4
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_not_xor_with_wrong_bool_contents
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; Even though bit 0 of the constant is 1, we require zero in the upper bits
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; for our aarch64's zero-or-one boolean contents.
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; CHECK-LABEL: name: icmp_not_xor_with_wrong_bool_contents
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
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; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C1]]
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; CHECK: $w0 = COPY [[XOR]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(s32) = G_CONSTANT i32 7
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%3:_(s32) = G_ICMP intpred(sgt), %0(s64), %1
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%4:_(s32) = G_XOR %3, %2
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_multiple_use
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_multiple_use
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]
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; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C1]]
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; CHECK: %other_use:_(s1) = G_AND [[ICMP]], [[C1]]
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; CHECK: %other_use_ext:_(s32) = G_ANYEXT %other_use(s1)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: $w1 = COPY %other_use_ext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s64) = COPY $x0
|
||||
%1:_(s64) = G_CONSTANT i64 1
|
||||
%2:_(s1) = G_CONSTANT i1 1
|
||||
%3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
|
||||
%4:_(s1) = G_XOR %3, %2
|
||||
%other_use:_(s1) = G_AND %3, %2
|
||||
%other_use_ext:_(s32) = G_ANYEXT %other_use(s1)
|
||||
%5:_(s32) = G_ANYEXT %4
|
||||
$w0 = COPY %5(s32)
|
||||
$w1 = COPY %other_use_ext
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: icmp_vector
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: $q0
|
||||
|
||||
; CHECK-LABEL: name: icmp_vector
|
||||
; CHECK: liveins: $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
|
||||
; CHECK: %splat_op2:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s1>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), %splat_op2
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[ICMP]](<4 x s1>)
|
||||
; CHECK: $q0 = COPY [[ANYEXT]](<4 x s32>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%0:_(<4 x s32>) = COPY $q0
|
||||
%1:_(s32) = G_CONSTANT i32 5
|
||||
%splat_op2:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %1, %1
|
||||
%2:_(s1) = G_CONSTANT i1 1
|
||||
%splat_true:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2
|
||||
%3:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %splat_op2
|
||||
%4:_(<4 x s1>) = G_XOR %3, %splat_true
|
||||
%5:_(<4 x s32>) = G_ANYEXT %4
|
||||
$q0 = COPY %5(<4 x s32>)
|
||||
RET_ReallyLR implicit $q0
|
||||
...
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||||
---
|
||||
name: condbr_of_not
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
liveins:
|
||||
- { reg: '$x0' }
|
||||
body: |
|
||||
; CHECK-LABEL: name: condbr_of_not
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||||
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
|
||||
; CHECK: TBZW [[LDRBBui]], 0, %bb.2
|
||||
; CHECK: bb.1:
|
||||
; CHECK: RET_ReallyLR
|
||||
; CHECK: bb.2:
|
||||
; CHECK: RET_ReallyLR
|
||||
bb.1:
|
||||
successors: %bb.2, %bb.3
|
||||
liveins: $x0
|
||||
|
||||
%0:gpr(p0) = COPY $x0
|
||||
%8:gpr(s8) = G_LOAD %0(p0) :: (load 1)
|
||||
%4:gpr(s32) = G_ANYEXT %8(s8)
|
||||
%5:gpr(s32) = G_CONSTANT i32 1
|
||||
%6:gpr(s32) = G_XOR %4, %5
|
||||
%3:gpr(s1) = G_TRUNC %6(s32)
|
||||
G_BRCOND %3(s1), %bb.3
|
||||
|
||||
bb.2:
|
||||
RET_ReallyLR
|
||||
|
||||
bb.3:
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: condbr_of_not_64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
liveins:
|
||||
- { reg: '$x0' }
|
||||
body: |
|
||||
; CHECK-LABEL: name: condbr_of_not_64
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||||
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
|
||||
; CHECK: TBZX [[COPY1]], 0, %bb.2
|
||||
; CHECK: bb.1:
|
||||
; CHECK: RET_ReallyLR
|
||||
; CHECK: bb.2:
|
||||
; CHECK: RET_ReallyLR
|
||||
bb.1:
|
||||
successors: %bb.2, %bb.3
|
||||
liveins: $x0
|
||||
|
||||
%0:gpr(p0) = COPY $x0
|
||||
%8:gpr(s8) = G_LOAD %0(p0) :: (load 1)
|
||||
%4:gpr(s64) = G_ANYEXT %8(s8)
|
||||
%5:gpr(s64) = G_CONSTANT i64 1
|
||||
%6:gpr(s64) = G_XOR %4, %5
|
||||
%3:gpr(s1) = G_TRUNC %6(s64)
|
||||
G_BRCOND %3(s1), %bb.3
|
||||
|
||||
bb.2:
|
||||
RET_ReallyLR
|
||||
|
||||
bb.3:
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
|
|
@ -136,24 +136,27 @@ define void @constrained_if_register_class() {
|
|||
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CHECK-NEXT: s_cmp_lg_u32 s4, 0
|
||||
; CHECK-NEXT: s_cselect_b32 s4, 1, 0
|
||||
; CHECK-NEXT: s_xor_b32 s4, s4, -1
|
||||
; CHECK-NEXT: s_and_b32 s4, s4, 1
|
||||
; CHECK-NEXT: s_cmp_lg_u32 s4, 0
|
||||
; CHECK-NEXT: s_cbranch_scc1 BB4_6
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB4_6
|
||||
; CHECK-NEXT: ; %bb.1: ; %bb2
|
||||
; CHECK-NEXT: s_getpc_b64 s[6:7]
|
||||
; CHECK-NEXT: s_add_u32 s6, s6, const.ptr@gotpcrel32@lo+4
|
||||
; CHECK-NEXT: s_addc_u32 s7, s7, const.ptr@gotpcrel32@hi+4
|
||||
; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
|
||||
; CHECK-NEXT: s_mov_b32 s4, -1
|
||||
; CHECK-NEXT: s_getpc_b64 s[4:5]
|
||||
; CHECK-NEXT: s_add_u32 s4, s4, const.ptr@gotpcrel32@lo+4
|
||||
; CHECK-NEXT: s_addc_u32 s5, s5, const.ptr@gotpcrel32@hi+4
|
||||
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, 1
|
||||
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
|
||||
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||||
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s6
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s7
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s5
|
||||
; CHECK-NEXT: flat_load_dword v0, v[0:1]
|
||||
; CHECK-NEXT: s_mov_b32 s4, -1
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, 1.0, v0
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
|
||||
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0
|
||||
; CHECK-NEXT: s_xor_b64 s[8:9], vcc, s[6:7]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
|
||||
; CHECK-NEXT: ; %bb.2: ; %bb7
|
||||
; CHECK-NEXT: s_mov_b32 s4, 0
|
||||
; CHECK-NEXT: ; %bb.3: ; %bb8
|
||||
|
|
@ -214,8 +217,10 @@ define amdgpu_kernel void @break_loop(i32 %arg) {
|
|||
; CHECK-NEXT: ; %bb.2: ; %bb4
|
||||
; CHECK-NEXT: ; in Loop: Header=BB5_1 Depth=1
|
||||
; CHECK-NEXT: global_load_dword v2, v[0:1], off
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2
|
||||
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, v0, v2
|
||||
; CHECK-NEXT: s_xor_b64 s[2:3], vcc, s[2:3]
|
||||
; CHECK-NEXT: BB5_3: ; %Flow
|
||||
; CHECK-NEXT: ; in Loop: Header=BB5_1 Depth=1
|
||||
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@ define i64 @v_sdiv_i64(i64 %num, i64 %den) {
|
|||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_or_b32_e32 v5, v1, v3
|
||||
; CHECK-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB0_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_ashrrev_i32_e32 v4, 31, v3
|
||||
|
|
@ -202,7 +204,10 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: s_mov_b32 s0, 0
|
||||
; CHECK-NEXT: s_mov_b32 s1, -1
|
||||
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1]
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e64 s[6:7], s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 vcc, s[6:7], s[8:9]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: s_cbranch_vccz BB1_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: s_ashr_i32 s6, s3, 31
|
||||
|
|
@ -353,14 +358,11 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_xor_b32_e32 v0, s0, v0
|
||||
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
|
||||
; CHECK-NEXT: s_mov_b32 s1, 0
|
||||
; CHECK-NEXT: s_branch BB1_3
|
||||
; CHECK-NEXT: BB1_2:
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: BB1_3: ; %Flow
|
||||
; CHECK-NEXT: BB1_2: ; %Flow
|
||||
; CHECK-NEXT: s_and_b32 s0, s1, 1
|
||||
; CHECK-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_5
|
||||
; CHECK-NEXT: ; %bb.4:
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_4
|
||||
; CHECK-NEXT: ; %bb.3:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
|
||||
; CHECK-NEXT: s_sub_i32 s0, 0, s4
|
||||
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
|
||||
|
|
@ -380,7 +382,7 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
|
||||
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
|
||||
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; CHECK-NEXT: BB1_5:
|
||||
; CHECK-NEXT: BB1_4:
|
||||
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; CHECK-NEXT: s_mov_b32 s1, s0
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
|
|
@ -693,10 +695,12 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v8, v0
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v9, v5
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5
|
||||
|
|
@ -870,10 +874,12 @@ define <2 x i64> @v_sdiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v7
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v7
|
||||
|
|
@ -2507,10 +2513,12 @@ define i64 @v_sdiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
|
|||
; CHECK-NEXT: v_lshl_b64 v[4:5], s[4:5], v2
|
||||
; CHECK-NEXT: v_mov_b32_e32 v2, 0
|
||||
; CHECK-NEXT: v_or_b32_e32 v3, v1, v5
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB7_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v5
|
||||
|
|
@ -2994,11 +3002,13 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v5, v0
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v7, v11
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_lshl_b64 v[8:9], s[4:5], v6
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v11
|
||||
|
|
@ -3172,10 +3182,12 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v9
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v9
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@ define i64 @v_srem_i64(i64 %num, i64 %den) {
|
|||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_or_b32_e32 v5, v1, v3
|
||||
; CHECK-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB0_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_ashrrev_i32_e32 v4, 31, v3
|
||||
|
|
@ -198,7 +200,10 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: s_mov_b32 s0, 0
|
||||
; CHECK-NEXT: s_mov_b32 s1, -1
|
||||
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1]
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e64 s[6:7], s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 vcc, s[6:7], s[8:9]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: s_cbranch_vccz BB1_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: s_ashr_i32 s0, s5, 31
|
||||
|
|
@ -347,14 +352,11 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_xor_b32_e32 v0, s6, v0
|
||||
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
|
||||
; CHECK-NEXT: s_mov_b32 s1, 0
|
||||
; CHECK-NEXT: s_branch BB1_3
|
||||
; CHECK-NEXT: BB1_2:
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: BB1_3: ; %Flow
|
||||
; CHECK-NEXT: BB1_2: ; %Flow
|
||||
; CHECK-NEXT: s_and_b32 s0, s1, 1
|
||||
; CHECK-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_5
|
||||
; CHECK-NEXT: ; %bb.4:
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_4
|
||||
; CHECK-NEXT: ; %bb.3:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4
|
||||
; CHECK-NEXT: s_sub_i32 s0, 0, s4
|
||||
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
|
||||
|
|
@ -372,7 +374,7 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
|
||||
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
|
||||
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
|
||||
; CHECK-NEXT: BB1_5:
|
||||
; CHECK-NEXT: BB1_4:
|
||||
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; CHECK-NEXT: s_mov_b32 s1, s0
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
|
|
@ -681,10 +683,12 @@ define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v8, v0
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v9, v5
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5
|
||||
|
|
@ -854,10 +858,12 @@ define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v7
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v7
|
||||
|
|
@ -2471,10 +2477,12 @@ define i64 @v_srem_i64_pow2_shl_denom(i64 %x, i64 %y) {
|
|||
; CHECK-NEXT: v_lshl_b64 v[4:5], s[4:5], v2
|
||||
; CHECK-NEXT: v_mov_b32_e32 v2, 0
|
||||
; CHECK-NEXT: v_or_b32_e32 v3, v1, v5
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB7_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v5
|
||||
|
|
@ -2950,11 +2958,13 @@ define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v5, v0
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v7, v11
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_lshl_b64 v[8:9], s[4:5], v6
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v11
|
||||
|
|
@ -3124,10 +3134,12 @@ define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v9
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v9
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
|
|||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_or_b32_e32 v5, v1, v3
|
||||
; CHECK-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB0_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v4, v2
|
||||
|
|
@ -187,7 +189,10 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: s_mov_b32 s4, 0
|
||||
; CHECK-NEXT: s_mov_b32 s5, -1
|
||||
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e64 s[6:7], s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 vcc, s[6:7], s[8:9]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: s_cbranch_vccz BB1_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
|
||||
|
|
@ -319,14 +324,11 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
|
||||
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
|
||||
; CHECK-NEXT: s_mov_b32 s5, 0
|
||||
; CHECK-NEXT: s_branch BB1_3
|
||||
; CHECK-NEXT: BB1_2:
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: BB1_3: ; %Flow
|
||||
; CHECK-NEXT: BB1_2: ; %Flow
|
||||
; CHECK-NEXT: s_and_b32 s1, s5, 1
|
||||
; CHECK-NEXT: s_cmp_lg_u32 s1, 0
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_5
|
||||
; CHECK-NEXT: ; %bb.4:
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_4
|
||||
; CHECK-NEXT: ; %bb.3:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
|
||||
; CHECK-NEXT: s_sub_i32 s1, 0, s2
|
||||
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
|
||||
|
|
@ -346,7 +348,7 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v0
|
||||
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
|
||||
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; CHECK-NEXT: BB1_5:
|
||||
; CHECK-NEXT: BB1_4:
|
||||
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; CHECK-NEXT: s_mov_b32 s1, s0
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
|
|
@ -629,10 +631,12 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v9, v1
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v9, v5
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
|
||||
|
|
@ -791,10 +795,12 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v7
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6
|
||||
|
|
@ -2286,13 +2292,15 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
|
|||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: s_movk_i32 s4, 0x1000
|
||||
; CHECK-NEXT: s_mov_b32 s5, 0
|
||||
; CHECK-NEXT: v_mov_b32_e32 v6, 0
|
||||
; CHECK-NEXT: v_lshl_b64 v[4:5], s[4:5], v2
|
||||
; CHECK-NEXT: v_or_b32_e32 v3, v1, v5
|
||||
; CHECK-NEXT: v_mov_b32_e32 v2, 0
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
|
||||
; CHECK-NEXT: v_or_b32_e32 v7, v1, v5
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB7_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v4
|
||||
|
|
@ -2728,14 +2736,16 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v7, v1
|
||||
; CGP-NEXT: s_movk_i32 s4, 0x1000
|
||||
; CGP-NEXT: s_mov_b32 s5, 0
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v4
|
||||
; CGP-NEXT: v_lshl_b64 v[8:9], s[4:5], v6
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v7, v11
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v10
|
||||
|
|
@ -2894,10 +2904,12 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v9
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v8
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
|
|||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_or_b32_e32 v5, v1, v3
|
||||
; CHECK-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB0_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v4, v2
|
||||
|
|
@ -184,7 +186,10 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: s_mov_b32 s4, 0
|
||||
; CHECK-NEXT: s_mov_b32 s5, -1
|
||||
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e64 s[6:7], s[6:7], 0
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 vcc, s[6:7], s[8:9]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: s_cbranch_vccz BB1_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
|
||||
|
|
@ -315,14 +320,11 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
|
||||
; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; CHECK-NEXT: s_mov_b32 s5, 0
|
||||
; CHECK-NEXT: s_branch BB1_3
|
||||
; CHECK-NEXT: BB1_2:
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CHECK-NEXT: BB1_3: ; %Flow
|
||||
; CHECK-NEXT: BB1_2: ; %Flow
|
||||
; CHECK-NEXT: s_and_b32 s1, s5, 1
|
||||
; CHECK-NEXT: s_cmp_lg_u32 s1, 0
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_5
|
||||
; CHECK-NEXT: ; %bb.4:
|
||||
; CHECK-NEXT: s_cbranch_scc0 BB1_4
|
||||
; CHECK-NEXT: ; %bb.3:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
|
||||
; CHECK-NEXT: s_sub_i32 s1, 0, s2
|
||||
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
|
||||
|
|
@ -340,7 +342,7 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
|
|||
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s2, v0
|
||||
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
|
||||
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
|
||||
; CHECK-NEXT: BB1_5:
|
||||
; CHECK-NEXT: BB1_4:
|
||||
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
|
||||
; CHECK-NEXT: s_mov_b32 s1, s0
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
|
|
@ -621,10 +623,12 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v9, v1
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v9, v5
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
|
||||
|
|
@ -780,10 +784,12 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v7
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB2_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6
|
||||
|
|
@ -2252,13 +2258,15 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
|
|||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: s_movk_i32 s4, 0x1000
|
||||
; CHECK-NEXT: s_mov_b32 s5, 0
|
||||
; CHECK-NEXT: v_mov_b32_e32 v6, 0
|
||||
; CHECK-NEXT: v_lshl_b64 v[4:5], s[4:5], v2
|
||||
; CHECK-NEXT: v_or_b32_e32 v3, v1, v5
|
||||
; CHECK-NEXT: v_mov_b32_e32 v2, 0
|
||||
; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
|
||||
; CHECK-NEXT: v_or_b32_e32 v7, v1, v5
|
||||
; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CHECK-NEXT: s_cbranch_execz BB7_2
|
||||
; CHECK-NEXT: ; %bb.1:
|
||||
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v4
|
||||
|
|
@ -2689,14 +2697,16 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: v_mov_b32_e32 v7, v1
|
||||
; CGP-NEXT: s_movk_i32 s4, 0x1000
|
||||
; CGP-NEXT: s_mov_b32 s5, 0
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_lshl_b64 v[10:11], s[4:5], v4
|
||||
; CGP-NEXT: v_lshl_b64 v[8:9], s[4:5], v6
|
||||
; CGP-NEXT: v_or_b32_e32 v1, v7, v11
|
||||
; CGP-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_2
|
||||
; CGP-NEXT: ; %bb.1:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v10
|
||||
|
|
@ -2852,10 +2862,12 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
|
|||
; CGP-NEXT: s_or_b64 exec, exec, s[4:5]
|
||||
; CGP-NEXT: v_or_b32_e32 v5, v3, v9
|
||||
; CGP-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CGP-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
|
||||
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, 1
|
||||
; CGP-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
|
||||
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
|
||||
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
|
||||
; CGP-NEXT: s_cbranch_execz BB8_6
|
||||
; CGP-NEXT: ; %bb.5:
|
||||
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v8
|
||||
|
|
|
|||
Loading…
Reference in New Issue