forked from OSchip/llvm-project
Remove some now-unneeded casts from instruction patterns. With the casts
removed, tblgen produces identical output to with them in. llvm-svn: 28867
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@ -546,7 +546,7 @@ def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
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def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
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def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
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// Loads.
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// Loads.
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def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
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def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
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// Stores.
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// Stores.
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def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
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def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
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@ -594,29 +594,29 @@ def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
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(VMRGHW VRRC:$vA, VRRC:$vA)>;
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(VMRGHW VRRC:$vA, VRRC:$vA)>;
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// Logical Operations
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// Logical Operations
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def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
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def : Pat<(v4i32 (vnot VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
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def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
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def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
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def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),
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def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),
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(v4i32 (VNOR VRRC:$A, VRRC:$B))>;
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(VNOR VRRC:$A, VRRC:$B)>;
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def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))),
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def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))),
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(v4i32 (VANDC VRRC:$A, VRRC:$B))>;
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(VANDC VRRC:$A, VRRC:$B)>;
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def : Pat<(fmul VRRC:$vA, VRRC:$vB),
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def : Pat<(fmul VRRC:$vA, VRRC:$vB),
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(v4f32 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0))))>;
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(VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>;
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// Fused multiply add and multiply sub for packed float. These are represented
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// Fused multiply add and multiply sub for packed float. These are represented
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// separately from the real instructions above, for operations that must have
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// separately from the real instructions above, for operations that must have
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// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
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// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
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def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(v4f32 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C))>;
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(v4f32 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C))>;
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(v4f32 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C))>;
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(v4f32 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C))>;
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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(VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;
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@ -490,7 +490,7 @@ def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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[(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
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[(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
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def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"xor $rA, $rS, $rB", IntGeneral,
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"xor $rA, $rS, $rB", IntGeneral,
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[(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
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[(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
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def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB", IntGeneral,
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"slw $rA, $rS, $rB", IntGeneral,
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[(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
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[(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
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@ -936,25 +936,25 @@ def : Pat<(srl GPRC:$rS, GPRC:$rB),
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def : Pat<(shl GPRC:$rS, GPRC:$rB),
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def : Pat<(shl GPRC:$rS, GPRC:$rB),
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(SLW GPRC:$rS, GPRC:$rB)>;
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(SLW GPRC:$rS, GPRC:$rB)>;
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def : Pat<(i32 (zextload iaddr:$src, i1)),
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def : Pat<(zextload iaddr:$src, i1),
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(LBZ iaddr:$src)>;
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(LBZ iaddr:$src)>;
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def : Pat<(i32 (zextload xaddr:$src, i1)),
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def : Pat<(zextload xaddr:$src, i1),
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(LBZX xaddr:$src)>;
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(LBZX xaddr:$src)>;
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def : Pat<(i32 (extload iaddr:$src, i1)),
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def : Pat<(extload iaddr:$src, i1),
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(LBZ iaddr:$src)>;
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(LBZ iaddr:$src)>;
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def : Pat<(i32 (extload xaddr:$src, i1)),
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def : Pat<(extload xaddr:$src, i1),
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(LBZX xaddr:$src)>;
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(LBZX xaddr:$src)>;
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def : Pat<(i32 (extload iaddr:$src, i8)),
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def : Pat<(extload iaddr:$src, i8),
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(LBZ iaddr:$src)>;
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(LBZ iaddr:$src)>;
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def : Pat<(i32 (extload xaddr:$src, i8)),
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def : Pat<(extload xaddr:$src, i8),
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(LBZX xaddr:$src)>;
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(LBZX xaddr:$src)>;
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def : Pat<(i32 (extload iaddr:$src, i16)),
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def : Pat<(extload iaddr:$src, i16),
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(LHZ iaddr:$src)>;
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(LHZ iaddr:$src)>;
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def : Pat<(i32 (extload xaddr:$src, i16)),
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def : Pat<(extload xaddr:$src, i16),
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(LHZX xaddr:$src)>;
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(LHZX xaddr:$src)>;
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def : Pat<(f64 (extload iaddr:$src, f32)),
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def : Pat<(extload iaddr:$src, f32),
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(FMRSD (LFS iaddr:$src))>;
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(FMRSD (LFS iaddr:$src))>;
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def : Pat<(f64 (extload xaddr:$src, f32)),
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def : Pat<(extload xaddr:$src, f32),
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(FMRSD (LFSX xaddr:$src))>;
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(FMRSD (LFSX xaddr:$src))>;
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include "PPCInstrAltivec.td"
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include "PPCInstrAltivec.td"
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