From 868783e85557dde30923fab94c7ffabf5e271818 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Fri, 13 Oct 2017 21:02:16 +0000 Subject: [PATCH] LowerTypeTests: Give imported symbols a type with size 0 so that they are not assumed not to alias. It is possible for both a base and a derived class to be satisfied with a unique vtable. If a program contains casts of the same pointer to both of those types, the CFI checks will be lowered to this (with ThinLTO): if (p != &__typeid_base_global_addr) trap(); if (p != &__typeid_derived_global_addr) trap(); The optimizer may then use the first condition combined with the assumption that __typeid_base_global_addr and __typeid_derived_global_addr may not alias to optimize away the second comparison, resulting in an unconditional trap. This patch fixes the bug by giving imported globals the type [0 x i8]*, which prevents the optimizer from assuming that they do not alias. Differential Revision: https://reviews.llvm.org/D38873 llvm-svn: 315753 --- compiler-rt/test/cfi/vtable-may-alias.cpp | 25 ++++ llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 8 +- llvm/test/Transforms/LowerTypeTests/import.ll | 112 +++++++++--------- .../Transforms/LowerTypeTests/simplify.ll | 12 +- 4 files changed, 93 insertions(+), 64 deletions(-) create mode 100644 compiler-rt/test/cfi/vtable-may-alias.cpp diff --git a/compiler-rt/test/cfi/vtable-may-alias.cpp b/compiler-rt/test/cfi/vtable-may-alias.cpp new file mode 100644 index 000000000000..f63b53b8c9e6 --- /dev/null +++ b/compiler-rt/test/cfi/vtable-may-alias.cpp @@ -0,0 +1,25 @@ +// RUN: %clangxx_cfi -o %t %s +// RUN: %run %t + +// In this example, both __typeid_A_global_addr and __typeid_B_global_addr will +// refer to the same address. Make sure that the compiler does not assume that +// they do not alias. + +struct A { + virtual void f() = 0; +}; + +struct B : A { + virtual void f() {} +}; + +__attribute__((weak)) void foo(void *p) { + B *b = (B *)p; + A *a = (A *)b; + a->f(); +} + +int main() { + B b; + foo(&b); +} diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp index 027f426649c4..ab205f4285e5 100644 --- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp +++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp @@ -259,6 +259,7 @@ class LowerTypeTestsModule { IntegerType *Int1Ty = Type::getInt1Ty(M.getContext()); IntegerType *Int8Ty = Type::getInt8Ty(M.getContext()); PointerType *Int8PtrTy = Type::getInt8PtrTy(M.getContext()); + ArrayType *Int8Arr0Ty = ArrayType::get(Type::getInt8Ty(M.getContext()), 0); IntegerType *Int32Ty = Type::getInt32Ty(M.getContext()); PointerType *Int32PtrTy = PointerType::getUnqual(Int32Ty); IntegerType *Int64Ty = Type::getInt64Ty(M.getContext()); @@ -803,10 +804,13 @@ LowerTypeTestsModule::importTypeId(StringRef TypeId) { TIL.TheKind = TTRes.TheKind; auto ImportGlobal = [&](StringRef Name) { - Constant *C = - M.getOrInsertGlobal(("__typeid_" + TypeId + "_" + Name).str(), Int8Ty); + // Give the global a type of length 0 so that it is not assumed not to alias + // with any other global. + Constant *C = M.getOrInsertGlobal(("__typeid_" + TypeId + "_" + Name).str(), + Int8Arr0Ty); if (auto *GV = dyn_cast(C)) GV->setVisibility(GlobalValue::HiddenVisibility); + C = ConstantExpr::getBitCast(C, Int8PtrTy); return C; }; diff --git a/llvm/test/Transforms/LowerTypeTests/import.ll b/llvm/test/Transforms/LowerTypeTests/import.ll index f397fa7c7b87..9746a98154f9 100644 --- a/llvm/test/Transforms/LowerTypeTests/import.ll +++ b/llvm/test/Transforms/LowerTypeTests/import.ll @@ -5,42 +5,42 @@ target datalayout = "e-p:64:64" declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone -; CHECK-DAG: @__typeid_single_global_addr = external hidden global i8 -; CHECK-DAG: @__typeid_inline6_global_addr = external hidden global i8 -; X86-DAG: @__typeid_inline6_align = external hidden global i8, !absolute_symbol !0 -; X86-DAG: @__typeid_inline6_size_m1 = external hidden global i8, !absolute_symbol !1 -; X86-DAG: @__typeid_inline6_inline_bits = external hidden global i8, !absolute_symbol !2 -; CHECK-DAG: @__typeid_inline5_global_addr = external hidden global i8 -; X86-DAG: @__typeid_inline5_align = external hidden global i8, !absolute_symbol !0 -; X86-DAG: @__typeid_inline5_size_m1 = external hidden global i8, !absolute_symbol !3 -; X86-DAG: @__typeid_inline5_inline_bits = external hidden global i8, !absolute_symbol !4 -; CHECK-DAG: @__typeid_bytearray32_global_addr = external hidden global i8 -; X86-DAG: @__typeid_bytearray32_align = external hidden global i8, !absolute_symbol !0 -; X86-DAG: @__typeid_bytearray32_size_m1 = external hidden global i8, !absolute_symbol !4 -; CHECK-DAG: @__typeid_bytearray32_byte_array = external hidden global i8 -; X86-DAG: @__typeid_bytearray32_bit_mask = external hidden global i8, !absolute_symbol !0 -; CHECK-DAG: @__typeid_bytearray7_global_addr = external hidden global i8 -; X86-DAG: @__typeid_bytearray7_align = external hidden global i8, !absolute_symbol !0 -; X86-DAG: @__typeid_bytearray7_size_m1 = external hidden global i8, !absolute_symbol !5 -; CHECK-DAG: @__typeid_bytearray7_byte_array = external hidden global i8 -; X86-DAG: @__typeid_bytearray7_bit_mask = external hidden global i8, !absolute_symbol !0 -; CHECK-DAG: @__typeid_allones32_global_addr = external hidden global i8 -; X86-DAG: @__typeid_allones32_align = external hidden global i8, !absolute_symbol !0 -; X86-DAG: @__typeid_allones32_size_m1 = external hidden global i8, !absolute_symbol !4 -; CHECK-DAG: @__typeid_allones7_global_addr = external hidden global i8 -; X86-DAG: @__typeid_allones7_align = external hidden global i8, !absolute_symbol !0 -; X86-DAG: @__typeid_allones7_size_m1 = external hidden global i8, !absolute_symbol !5 +; CHECK-DAG: @__typeid_single_global_addr = external hidden global [0 x i8] +; CHECK-DAG: @__typeid_inline6_global_addr = external hidden global [0 x i8] +; X86-DAG: @__typeid_inline6_align = external hidden global [0 x i8], !absolute_symbol !0 +; X86-DAG: @__typeid_inline6_size_m1 = external hidden global [0 x i8], !absolute_symbol !1 +; X86-DAG: @__typeid_inline6_inline_bits = external hidden global [0 x i8], !absolute_symbol !2 +; CHECK-DAG: @__typeid_inline5_global_addr = external hidden global [0 x i8] +; X86-DAG: @__typeid_inline5_align = external hidden global [0 x i8], !absolute_symbol !0 +; X86-DAG: @__typeid_inline5_size_m1 = external hidden global [0 x i8], !absolute_symbol !3 +; X86-DAG: @__typeid_inline5_inline_bits = external hidden global [0 x i8], !absolute_symbol !4 +; CHECK-DAG: @__typeid_bytearray32_global_addr = external hidden global [0 x i8] +; X86-DAG: @__typeid_bytearray32_align = external hidden global [0 x i8], !absolute_symbol !0 +; X86-DAG: @__typeid_bytearray32_size_m1 = external hidden global [0 x i8], !absolute_symbol !4 +; CHECK-DAG: @__typeid_bytearray32_byte_array = external hidden global [0 x i8] +; X86-DAG: @__typeid_bytearray32_bit_mask = external hidden global [0 x i8], !absolute_symbol !0 +; CHECK-DAG: @__typeid_bytearray7_global_addr = external hidden global [0 x i8] +; X86-DAG: @__typeid_bytearray7_align = external hidden global [0 x i8], !absolute_symbol !0 +; X86-DAG: @__typeid_bytearray7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5 +; CHECK-DAG: @__typeid_bytearray7_byte_array = external hidden global [0 x i8] +; X86-DAG: @__typeid_bytearray7_bit_mask = external hidden global [0 x i8], !absolute_symbol !0 +; CHECK-DAG: @__typeid_allones32_global_addr = external hidden global [0 x i8] +; X86-DAG: @__typeid_allones32_align = external hidden global [0 x i8], !absolute_symbol !0 +; X86-DAG: @__typeid_allones32_size_m1 = external hidden global [0 x i8], !absolute_symbol !4 +; CHECK-DAG: @__typeid_allones7_global_addr = external hidden global [0 x i8] +; X86-DAG: @__typeid_allones7_align = external hidden global [0 x i8], !absolute_symbol !0 +; X86-DAG: @__typeid_allones7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5 ; CHECK: define i1 @allones7(i8* [[p:%.*]]) define i1 @allones7(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_allones7_global_addr to i64) - ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_allones7_align to i8) to i64) - ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_allones7_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_allones7_global_addr to i64) + ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_allones7_align to i8) to i64) + ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_allones7_align to i8)) to i64) ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 1 ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 63 ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_allones7_size_m1 to i64) + ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_allones7_size_m1 to i64) ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 42 ; CHECK-NEXT: ret i1 [[ule]] %x = call i1 @llvm.type.test(i8* %p, metadata !"allones7") @@ -50,13 +50,13 @@ define i1 @allones7(i8* %p) { ; CHECK: define i1 @allones32(i8* [[p:%.*]]) define i1 @allones32(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_allones32_global_addr to i64) - ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_allones32_align to i8) to i64) - ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_allones32_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_allones32_global_addr to i64) + ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_allones32_align to i8) to i64) + ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_allones32_align to i8)) to i64) ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 2 ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 62 ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_allones32_size_m1 to i64) + ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_allones32_size_m1 to i64) ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 12345 ; CHECK-NEXT: ret i1 [[ule]] %x = call i1 @llvm.type.test(i8* %p, metadata !"allones32") @@ -66,20 +66,20 @@ define i1 @allones32(i8* %p) { ; CHECK: define i1 @bytearray7(i8* [[p:%.*]]) define i1 @bytearray7(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_bytearray7_global_addr to i64) - ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_bytearray7_align to i8) to i64) - ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_bytearray7_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_bytearray7_global_addr to i64) + ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8) to i64) + ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8)) to i64) ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 3 ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 61 ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_bytearray7_size_m1 to i64) + ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_bytearray7_size_m1 to i64) ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 43 ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]] ; CHECK: [[t]]: - ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* @__typeid_bytearray7_byte_array, i64 [[or]] + ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @__typeid_bytearray7_byte_array, i32 0, i32 0), i64 [[or]] ; CHECK-NEXT: [[load:%.*]] = load i8, i8* [[gep]] - ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* @__typeid_bytearray7_bit_mask to i8) + ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint ([0 x i8]* @__typeid_bytearray7_bit_mask to i8) ; ARM-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* inttoptr (i64 64 to i8*) to i8) ; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0 ; CHECK-NEXT: br label %[[f]] @@ -94,20 +94,20 @@ define i1 @bytearray7(i8* %p) { ; CHECK: define i1 @bytearray32(i8* [[p:%.*]]) define i1 @bytearray32(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_bytearray32_global_addr to i64) - ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_bytearray32_align to i8) to i64) - ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_bytearray32_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_bytearray32_global_addr to i64) + ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_bytearray32_align to i8) to i64) + ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_bytearray32_align to i8)) to i64) ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 4 ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 60 ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_bytearray32_size_m1 to i64) + ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_bytearray32_size_m1 to i64) ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 12346 ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]] ; CHECK: [[t]]: - ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* @__typeid_bytearray32_byte_array, i64 [[or]] + ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @__typeid_bytearray32_byte_array, i32 0, i32 0), i64 [[or]] ; CHECK-NEXT: [[load:%.*]] = load i8, i8* [[gep]] - ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* @__typeid_bytearray32_bit_mask to i8) + ; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint ([0 x i8]* @__typeid_bytearray32_bit_mask to i8) ; ARM-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* inttoptr (i64 128 to i8*) to i8) ; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0 ; CHECK-NEXT: br label %[[f]] @@ -122,13 +122,13 @@ define i1 @bytearray32(i8* %p) { ; CHECK: define i1 @inline5(i8* [[p:%.*]]) define i1 @inline5(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_inline5_global_addr to i64) - ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_inline5_align to i8) to i64) - ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_inline5_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_inline5_global_addr to i64) + ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_inline5_align to i8) to i64) + ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_inline5_align to i8)) to i64) ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 5 ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 59 ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_inline5_size_m1 to i64) + ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_inline5_size_m1 to i64) ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 31 ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]] @@ -136,7 +136,7 @@ define i1 @inline5(i8* %p) { ; CHECK-NEXT: [[trunc:%.*]] = trunc i64 [[or]] to i32 ; CHECK-NEXT: [[and:%.*]] = and i32 [[trunc]], 31 ; CHECK-NEXT: [[shl2:%.*]] = shl i32 1, [[and]] - ; X86-NEXT: [[and2:%.*]] = and i32 ptrtoint (i8* @__typeid_inline5_inline_bits to i32), [[shl2]] + ; X86-NEXT: [[and2:%.*]] = and i32 ptrtoint ([0 x i8]* @__typeid_inline5_inline_bits to i32), [[shl2]] ; ARM-NEXT: [[and2:%.*]] = and i32 123, [[shl2]] ; CHECK-NEXT: [[ne:%.*]] = icmp ne i32 [[and2]], 0 ; CHECK-NEXT: br label %[[f]] @@ -151,20 +151,20 @@ define i1 @inline5(i8* %p) { ; CHECK: define i1 @inline6(i8* [[p:%.*]]) define i1 @inline6(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_inline6_global_addr to i64) - ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_inline6_align to i8) to i64) - ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_inline6_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_inline6_global_addr to i64) + ; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_inline6_align to i8) to i64) + ; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_inline6_align to i8)) to i64) ; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 6 ; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 58 ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_inline6_size_m1 to i64) + ; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_inline6_size_m1 to i64) ; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 63 ; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]] ; CHECK: [[t]]: ; CHECK-NEXT: [[and:%.*]] = and i64 [[or]], 63 ; CHECK-NEXT: [[shl2:%.*]] = shl i64 1, [[and]] - ; X86-NEXT: [[and2:%.*]] = and i64 ptrtoint (i8* @__typeid_inline6_inline_bits to i64), [[shl2]] + ; X86-NEXT: [[and2:%.*]] = and i64 ptrtoint ([0 x i8]* @__typeid_inline6_inline_bits to i64), [[shl2]] ; ARM-NEXT: [[and2:%.*]] = and i64 1000000000000, [[shl2]] ; CHECK-NEXT: [[ne:%.*]] = icmp ne i64 [[and2]], 0 ; CHECK-NEXT: br label %[[f]] @@ -179,7 +179,7 @@ define i1 @inline6(i8* %p) { ; CHECK: define i1 @single(i8* [[p:%.*]]) define i1 @single(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[eq:%.*]] = icmp eq i64 [[pi]], ptrtoint (i8* @__typeid_single_global_addr to i64) + ; CHECK-NEXT: [[eq:%.*]] = icmp eq i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_single_global_addr to i64) ; CHECK-NEXT: ret i1 [[eq]] %x = call i1 @llvm.type.test(i8* %p, metadata !"single") ret i1 %x diff --git a/llvm/test/Transforms/LowerTypeTests/simplify.ll b/llvm/test/Transforms/LowerTypeTests/simplify.ll index 12249d9012ab..a189b9856dd0 100644 --- a/llvm/test/Transforms/LowerTypeTests/simplify.ll +++ b/llvm/test/Transforms/LowerTypeTests/simplify.ll @@ -8,17 +8,17 @@ declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone ; CHECK: define i1 @bytearray7(i8* [[p:%.*]]) define i1 @bytearray7(i8* %p) { ; CHECK-NEXT: [[pi:%.*]] = ptrtoint i8* [[p]] to i64 - ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (i8* @__typeid_bytearray7_global_addr to i64) - ; CHECK-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (i8* @__typeid_bytearray7_align to i8) to i64) - ; CHECK-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (i8* @__typeid_bytearray7_align to i8)) to i64) + ; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint ([0 x i8]* @__typeid_bytearray7_global_addr to i64) + ; CHECK-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8) to i64) + ; CHECK-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint ([0 x i8]* @__typeid_bytearray7_align to i8)) to i64) ; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]] - ; CHECK-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (i8* @__typeid_bytearray7_size_m1 to i64) + ; CHECK-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint ([0 x i8]* @__typeid_bytearray7_size_m1 to i64) ; CHECK-NEXT: br i1 [[ule]], label %[[t1:.*]], label %[[f:.*]] ; CHECK: [[t1]]: - ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* @__typeid_bytearray7_byte_array, i64 [[or]] + ; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, i8* getelementptr inbounds ([0 x i8], [0 x i8]* @__typeid_bytearray7_byte_array, i32 0, i32 0), i64 [[or]] ; CHECK-NEXT: [[load:%.*]] = load i8, i8* [[gep]] - ; CHECK-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (i8* @__typeid_bytearray7_bit_mask to i8) + ; CHECK-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint ([0 x i8]* @__typeid_bytearray7_bit_mask to i8) ; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0 ; CHECK-NEXT: br i1 [[ne]], label %[[t:.*]], label %[[f:.*]]