forked from OSchip/llvm-project
Add code to emulate SXTH Arm instruction.
llvm-svn: 126951
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@ -7499,6 +7499,91 @@ EmulateInstructionARM::EmulateSXTB (ARMEncoding encoding)
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return true;
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}
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// SXTH extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination
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// register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
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bool
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EmulateInstructionARM::EmulateSXTH (ARMEncoding encoding)
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{
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#if 0
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if ConditionPassed() then
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EncodingSpecificOperations();
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rotated = ROR(R[m], rotation);
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R[d] = SignExtend(rotated<15:0>, 32);
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t d;
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uint32_t m;
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uint32_t rotation;
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// EncodingSpecificOperations();
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switch (encoding)
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{
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case eEncodingT1:
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// d = UInt(Rd); m = UInt(Rm); rotation = 0;
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d = Bits32 (opcode, 2, 0);
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m = Bits32 (opcode, 5, 3);
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rotation = 0;
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break;
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case eEncodingT2:
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// d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:’000’);
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d = Bits32 (opcode, 11, 8);
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m = Bits32 (opcode, 3, 0);
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rotation = Bits32 (opcode, 5, 4) << 3;
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// if BadReg(d) || BadReg(m) then UNPREDICTABLE;
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if (BadReg (d) || BadReg (m))
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return false;
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break;
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case eEncodingA1:
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// d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:’000’);
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d = Bits32 (opcode, 15, 12);
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m = Bits32 (opcode, 3, 0);
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rotation = Bits32 (opcode, 11, 10) << 3;
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// if d == 15 || m == 15 then UNPREDICTABLE;
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if ((d == 15) || (m == 15))
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return false;
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break;
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default:
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return false;
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}
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uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
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if (!success)
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return false;
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// rotated = ROR(R[m], rotation);
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uint64_t rotated = ROR (Rm, rotation);
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// R[d] = SignExtend(rotated<15:0>, 32);
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Register source_reg;
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source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
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EmulateInstruction::Context context;
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context.type = eContextRegisterLoad;
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context.SetRegister (source_reg);
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uint64_t data = llvm::SignExtend64<16> (rotated);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, data))
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return false;
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}
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return true;
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}
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// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
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// and writes the result to the destination register. It can optionally update the condition flags based on
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// the result.
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@ -8894,7 +8979,8 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
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//----------------------------------------------------------------------
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// Other instructions
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//----------------------------------------------------------------------
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{ 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" }
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{ 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" },
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{ 0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}" }
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};
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static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
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@ -9169,7 +9255,9 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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// Other instructions
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//----------------------------------------------------------------------
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{ 0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>" },
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{ 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" }
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{ 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
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{ 0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>" },
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{ 0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}" }
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};
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