maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Revert a part of r126557 which could create unschedulable DAGs. 

llvm-svn: 134067
This commit is contained in:
Benjamin Kramer 2011-06-29 13:47:25 +00:00
parent 91f5b811ff
commit 8665f8d916
2 changed files with 0 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1310,16 +1310,6 @@ SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
return SDValue();
}
/// isCarryMaterialization - Returns true if V is an ADDE node that is known to
/// return 0 or 1 depending on the carry flag.
static bool isCarryMaterialization(SDValue V) {
if (V.getOpcode() != ISD::ADDE)
return false;
ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0));
return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1);
}
SDValue DAGCombiner::visitADD(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
@ -1483,18 +1473,6 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
}
// add (adde 0, 0, glue), X -> adde X, 0, glue
if (N0->hasOneUse() && isCarryMaterialization(N0))
return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0),
N0.getOperand(2));
// add X, (adde 0, 0, glue) -> adde X, 0, glue
if (N1->hasOneUse() && isCarryMaterialization(N1))
return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0),
N1.getOperand(2));
return SDValue();
}
@ -1538,16 +1516,6 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
N->getDebugLoc(), MVT::Glue));
}
// addc (adde 0, 0, glue), X -> adde X, 0, glue
if (N0->hasOneUse() && isCarryMaterialization(N0))
return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1,
DAG.getConstant(0, VT), N0.getOperand(2));
// addc X, (adde 0, 0, glue) -> adde X, 0, glue
if (N1->hasOneUse() && isCarryMaterialization(N1))
return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0,
DAG.getConstant(0, VT), N1.getOperand(2));
return SDValue();
}

6
llvm/test/CodeGen/X86/adde-carry.ll
View File

@ -1,5 +1,4 @@
; RUN: llc -march=x86-64 < %s | FileCheck %s -check-prefix=CHECK-64
; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=CHECK-32
define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind {
entry:
@ -16,11 +15,6 @@ entry:
store i64 %8, i64* %t, align 8
ret void
; CHECK-32: addl
; CHECK-32: adcl
; CHECK-32: adcl $0
; CHECK-32: adcl $0
; CHECK-64: addq
; CHECK-64: adcq $0
}