forked from OSchip/llvm-project
R600/SI: fix inserting waits for unordered defines
Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 176342
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@ -88,6 +88,9 @@ private:
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MachineBasicBlock::iterator I,
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const Counters &Counts);
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/// \brief Do we need def2def checks?
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bool unorderedDefines(MachineInstr &MI);
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/// \brief Resolve all operand dependencies to counter requirements
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Counters handleOperands(MachineInstr &MI);
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@ -125,7 +128,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
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// Only consider stores or EXP for EXP_CNT
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Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
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(MI.getOpcode() == AMDGPU::EXP || !MI.getDesc().mayStore()));
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(MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
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// LGKM may uses larger values
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if (TSFlags & SIInstrFlags::LGKM_CNT) {
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@ -299,8 +302,21 @@ static void increaseCounters(Counters &Dst, const Counters &Src) {
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Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]);
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}
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bool SIInsertWaits::unorderedDefines(MachineInstr &MI) {
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uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
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if (TSFlags & SIInstrFlags::LGKM_CNT)
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return true;
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if (TSFlags & SIInstrFlags::EXP_CNT)
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return ExpInstrTypesSeen == 3;
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return false;
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}
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Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
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bool UnorderedDefines = unorderedDefines(MI);
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Counters Result = ZeroCounts;
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// For each register affected by this
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@ -311,8 +327,11 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
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RegInterval Interval = getRegInterval(Op);
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for (unsigned j = Interval.first; j < Interval.second; ++j) {
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if (Op.isDef())
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if (Op.isDef()) {
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increaseCounters(Result, UsedRegs[j]);
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if (UnorderedDefines)
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increaseCounters(Result, DefinedRegs[j]);
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}
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if (Op.isUse())
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increaseCounters(Result, DefinedRegs[j]);
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