forked from OSchip/llvm-project
Moves now select correct opcode based on the data size.
llvm-svn: 4981
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parent
1176170c16
commit
862f3ef8bc
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@ -23,7 +23,6 @@ X86RegisterInfo::X86RegisterInfo()
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: MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0])) {
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}
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MachineBasicBlock::iterator
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X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MBBI,
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@ -31,7 +30,15 @@ X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock *MBB,
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unsigned ImmOffset, unsigned dataSize)
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const
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{
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MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5),
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unsigned opcode;
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switch (dataSize) {
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case 1: opcode = X86::MOVrm8; break;
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case 2: opcode = X86::MOVrm16; break;
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case 4: opcode = X86::MOVrm32; break;
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default: assert(0 && "Invalid data size!");
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}
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MachineInstr *MI = addRegOffset(BuildMI(opcode, 5),
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DestReg, ImmOffset).addReg(SrcReg);
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return ++(MBB->insert(MBBI, MI));
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}
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@ -43,7 +50,15 @@ X86RegisterInfo::loadRegOffset2Reg(MachineBasicBlock *MBB,
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unsigned ImmOffset, unsigned dataSize)
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const
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{
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MachineInstr *MI = addRegOffset(BuildMI(X86::MOVmr32, 5).addReg(DestReg),
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unsigned opcode;
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switch (dataSize) {
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case 1: opcode = X86::MOVmr8; break;
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case 2: opcode = X86::MOVmr16; break;
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case 4: opcode = X86::MOVmr32; break;
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default: assert(0 && "Invalid data size!");
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}
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MachineInstr *MI = addRegOffset(BuildMI(opcode, 5).addReg(DestReg),
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SrcReg, ImmOffset);
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return ++(MBB->insert(MBBI, MI));
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}
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