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Fix merging base-updates for VLDM/VSTM: Before I switched these instructions 

to use AddrMode4, there was a count of the registers stored in one of the
operands.  I changed that to just count the operands but forgot to adjust for
the size of D registers.  This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.

llvm-svn: 113576
This commit is contained in:
Bob Wilson 2010-09-10 05:15:04 +00:00
parent 428a9a58fa
commit 8617234658
2 changed files with 7 additions and 2 deletions
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3
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -458,9 +458,10 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
case ARM::t2STM:
case ARM::VLDMS:
case ARM::VSTMS:
return (MI->getNumOperands() - 4) * 4;
case ARM::VLDMD:
case ARM::VSTMD:
return (MI->getNumOperands() - 4) * 4;
return (MI->getNumOperands() - 4) * 8;
}
}

6
llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
View File

@ -1,11 +1,15 @@
; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s
@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
; CHECK: dct_luma_sp:
define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
entry:
; Make sure to use base-updating stores for saving callee-saved registers.
; CHECK-NOT: sub sp
; CHECK: vstmdb sp!
%predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1]
br label %cond_next489