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[NFC][RISCV] Enable TuneNoDefaultUnroll feature to control targets which use default unroll preference 

In RISCVTargetTransformInfo, enumerating the processor family is not a good way to predict.
Because it needs to enumerate many subtarget family and is hard to update if add new subtarget.
Instead, create a feature to distinguish whether targets want to use default unroll preference or not.

Keep TuneSiFive7 because it's flag to indicate subtarget family, which may used in other place.

Differential Revision: https://reviews.llvm.org/D125741
This commit is contained in:
Zi Xuan Wu (Zeson) 2022-05-19 12:17:29 +08:00 committed by Zi Xuan Wu
parent 1351a9b19e
commit 861489af1b
3 changed files with 12 additions and 11 deletions
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14
llvm/lib/Target/RISCV/RISCV.td
View File

@ -430,6 +430,10 @@ foreach i = {1-31} in
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
"true", "Enable save/restore.">;
def TuneNoDefaultUnroll
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
"Disable default unroll preference.">;
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors">;
@ -465,9 +469,9 @@ def : ProcessorModel<"rocket-rv32", RocketModel, []>;
def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [],
[TuneSiFive7]>;
[TuneSiFive7, TuneNoDefaultUnroll]>;
def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit],
[TuneSiFive7]>;
[TuneSiFive7, TuneNoDefaultUnroll]>;
def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
FeatureStdExtC]>;
@ -494,7 +498,7 @@ def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtC],
[TuneSiFive7]>;
[TuneSiFive7, TuneNoDefaultUnroll]>;
def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
FeatureStdExtM,
@ -519,7 +523,7 @@ def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneSiFive7]>;
[TuneSiFive7, TuneNoDefaultUnroll]>;
def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
FeatureStdExtM,
@ -534,7 +538,7 @@ def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneSiFive7]>;
[TuneSiFive7, TuneNoDefaultUnroll]>;
//===----------------------------------------------------------------------===//
// Define the RISC-V target.

2
llvm/lib/Target/RISCV/RISCVSubtarget.h
View File

@ -90,6 +90,7 @@ private:
bool IsRV32E = false;
bool EnableLinkerRelax = false;
bool EnableRVCHintInstrs = true;
bool EnableDefaultUnroll = true;
bool EnableSaveRestore = false;
unsigned XLen = 32;
unsigned ZvlLen = 0;
@ -179,6 +180,7 @@ public:
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
bool enableDefaultUnroll() const { return EnableDefaultUnroll; }
bool enableSaveRestore() const { return EnableSaveRestore; }
MVT getXLenVT() const { return XLenVT; }
unsigned getXLen() const { return XLen; }

7
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
View File

@ -352,13 +352,8 @@ void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
// TODO: More tuning on benchmarks and metrics with changes as needed
// would apply to all settings below to enable performance.
// Support explicit targets enabled for SiFive with the unrolling preferences
// below
bool UseDefaultPreferences = true;
if (ST->getProcFamily() == RISCVSubtarget::SiFive7)
UseDefaultPreferences = false;
if (UseDefaultPreferences)
if (ST->enableDefaultUnroll())
return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE);
// Enable Upper bound unrolling universally, not dependant upon the conditions