forked from OSchip/llvm-project
[X86] Decode MPX BND registers.
We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427
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@ -1450,10 +1450,10 @@ static int readModRM(struct InternalInstruction* insn) {
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}
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#define GENERIC_FIXUP_FUNC(name, base, prefix) \
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static uint8_t name(struct InternalInstruction *insn, \
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OperandType type, \
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uint8_t index, \
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uint8_t *valid) { \
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static uint16_t name(struct InternalInstruction *insn, \
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OperandType type, \
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uint8_t index, \
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uint8_t *valid) { \
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*valid = 1; \
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switch (type) { \
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default: \
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@ -1503,6 +1503,10 @@ static int readModRM(struct InternalInstruction* insn) {
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return prefix##_DR0 + index; \
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case TYPE_CONTROLREG: \
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return prefix##_CR0 + index; \
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case TYPE_BNDR: \
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if (index > 3) \
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*valid = 0; \
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return prefix##_BND0 + index; \
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} \
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}
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@ -369,6 +369,12 @@ namespace X86Disassembler {
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ENTRY(CR14) \
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ENTRY(CR15)
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#define REGS_BOUND \
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ENTRY(BND0) \
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ENTRY(BND1) \
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ENTRY(BND2) \
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ENTRY(BND3)
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#define ALL_EA_BASES \
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EA_BASES_16BIT \
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EA_BASES_32BIT \
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@ -391,6 +397,7 @@ namespace X86Disassembler {
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REGS_SEGMENT \
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REGS_DEBUG \
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REGS_CONTROL \
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REGS_BOUND \
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ENTRY(RIP)
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/// \brief All possible values of the base field for effective-address
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@ -1,38 +1,41 @@
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// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s | FileCheck %s
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// RUN: llvm-mc -triple x86_64-- -mattr=+mpx --show-encoding %s |\
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// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING
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// RUN: llvm-mc -triple x86_64-- -mattr=+mpx -filetype=obj %s |\
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// RUN: llvm-objdump -d - -mattr=+mpx | FileCheck %s
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// CHECK: bndmk (%rax), %bnd0
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// CHECK: encoding: [0xf3,0x48,0x0f,0x1b,0x00]
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// ENCODING: encoding: [0xf3,0x48,0x0f,0x1b,0x00]
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bndmk (%rax), %bnd0
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// CHECK: bndmk 1024(%rax), %bnd1
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// CHECK: encoding: [0xf3,0x48,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
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// ENCODING: encoding: [0xf3,0x48,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
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bndmk 1024(%rax), %bnd1
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// CHECK: bndmov %bnd2, %bnd1
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// CHECK: encoding: [0x66,0x0f,0x1b,0xd1]
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// ENCODING: encoding: [0x66,0x0f,0x1b,0xd1]
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bndmov %bnd2, %bnd1
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// CHECK: bndmov %bnd1, 1024(%r9)
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// CHECK: encoding: [0x66,0x49,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
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// ENCODING: encoding: [0x66,0x49,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
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bndmov %bnd1, 1024(%r9)
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// CHECK: bndstx %bnd1, 1024(%rax)
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// CHECK: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
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// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
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bndstx %bnd1, 1024(%rax)
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// CHECK: bndldx 1024(%r8), %bnd1
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// CHECK: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
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// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
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bndldx 1024(%r8), %bnd1
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// CHECK: bndcl 121(%r10), %bnd1
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// CHECK: encoding: [0xf3,0x49,0x0f,0x1a,0x4a,0x79]
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// ENCODING: encoding: [0xf3,0x49,0x0f,0x1a,0x4a,0x79]
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bndcl 121(%r10), %bnd1
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// CHECK: bndcn 121(%rcx), %bnd3
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// CHECK: encoding: [0xf2,0x48,0x0f,0x1b,0x59,0x79]
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// ENCODING: encoding: [0xf2,0x48,0x0f,0x1b,0x59,0x79]
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bndcn 121(%rcx), %bnd3
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// CHECK: bndcu %rdx, %bnd3
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// CHECK: encoding: [0xf2,0x48,0x0f,0x1a,0xda]
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// ENCODING: encoding: [0xf2,0x48,0x0f,0x1a,0xda]
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bndcu %rdx, %bnd3
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