forked from OSchip/llvm-project
[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize
Changes the Offset arguments to both functions from int64_t to TypeSize & updates all uses of the functions to create the offset using TypeSize::Fixed() Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D85220
This commit is contained in:
Kerry McLaughlin
parent
b2b7dbb47a
commit
85c7e89f3b
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@ -870,7 +870,7 @@ public:
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/// Returns sum of the base pointer and offset.
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/// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
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SDValue getMemBasePlusOffset(SDValue Base, int64_t Offset, const SDLoc &DL,
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SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL,
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const SDNodeFlags Flags = SDNodeFlags());
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SDValue getMemBasePlusOffset(SDValue Base, SDValue Offset, const SDLoc &DL,
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const SDNodeFlags Flags = SDNodeFlags());
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@ -878,7 +878,7 @@ public:
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/// Create an add instruction with appropriate flags when used for
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/// addressing some offset of an object. i.e. if a load is split into multiple
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/// components, create an add nuw from the base pointer to the offset.
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SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, int64_t Offset) {
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SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) {
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(true);
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return getMemBasePlusOffset(Ptr, Offset, SL, Flags);
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@ -8560,8 +8560,8 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) {
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RHS->getAddressSpace(), NewAlign,
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RHS->getMemOperand()->getFlags(), &Fast) &&
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Fast) {
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SDValue NewPtr =
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DAG.getMemBasePlusOffset(RHS->getBasePtr(), PtrOff, DL);
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SDValue NewPtr = DAG.getMemBasePlusOffset(
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RHS->getBasePtr(), TypeSize::Fixed(PtrOff), DL);
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AddToWorklist(NewPtr.getNode());
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SDValue Load = DAG.getLoad(
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VT, DL, RHS->getChain(), NewPtr,
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@ -9733,7 +9733,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
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LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT, Align,
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LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
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BasePtr = DAG.getMemBasePlusOffset(BasePtr, Stride, DL);
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BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::Fixed(Stride), DL);
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Loads.push_back(SplitLoad.getValue(0));
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Chains.push_back(SplitLoad.getValue(1));
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@ -10954,8 +10954,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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// The original load itself didn't wrap, so an offset within it doesn't.
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(true);
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SDValue NewPtr =
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DAG.getMemBasePlusOffset(LN0->getBasePtr(), PtrOff, DL, Flags);
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SDValue NewPtr = DAG.getMemBasePlusOffset(LN0->getBasePtr(),
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TypeSize::Fixed(PtrOff), DL, Flags);
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AddToWorklist(NewPtr.getNode());
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SDValue Load;
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@ -15642,7 +15642,7 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
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SDValue Ptr = St->getBasePtr();
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if (StOffset) {
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SDLoc DL(IVal);
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Ptr = DAG.getMemBasePlusOffset(Ptr, StOffset, DL);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(StOffset), DL);
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NewAlign = MinAlign(NewAlign, StOffset);
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}
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@ -15756,7 +15756,8 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
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if (NewAlign < DAG.getDataLayout().getABITypeAlign(NewVTTy))
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return SDValue();
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SDValue NewPtr = DAG.getMemBasePlusOffset(Ptr, PtrOff, SDLoc(LD));
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SDValue NewPtr =
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DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(PtrOff), SDLoc(LD));
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SDValue NewLD =
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DAG.getLoad(NewVT, SDLoc(N0), LD->getChain(), NewPtr,
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LD->getPointerInfo().getWithOffset(PtrOff), NewAlign,
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@ -17002,7 +17003,7 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
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SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
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ST->getAlignment(), MMOFlags, AAInfo);
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Ptr = DAG.getMemBasePlusOffset(Ptr, 4, DL);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), DL);
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Alignment = MinAlign(Alignment, 4U);
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SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
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ST->getPointerInfo().getWithOffset(4),
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@ -17353,7 +17354,7 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
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// Lower value store.
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SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
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ST->getAlignment(), MMOFlags, AAInfo);
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Ptr = DAG.getMemBasePlusOffset(Ptr, HalfValBitSize / 8, DL);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(HalfValBitSize / 8), DL);
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// Higher value store.
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SDValue St1 =
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DAG.getStore(St0, DL, Hi, Ptr,
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@ -19361,7 +19362,8 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
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SDValue BaseAddr = Ld->getBasePtr();
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// TODO: Use "BaseIndexOffset" to make this more effective.
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SDValue NewAddr = DAG.getMemBasePlusOffset(BaseAddr, Offset, DL);
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SDValue NewAddr =
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DAG.getMemBasePlusOffset(BaseAddr, TypeSize::Fixed(Offset), DL);
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MachineFunction &MF = DAG.getMachineFunction();
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MachineMemOperand *MMO = MF.getMachineMemOperand(Ld->getMemOperand(), Offset,
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VT.getStoreSize());
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@ -470,7 +470,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(),
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ST->getOriginalAlign(), MMOFlags, AAInfo);
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Ptr = DAG.getMemBasePlusOffset(Ptr, 4, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), dl);
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Hi = DAG.getStore(Chain, dl, Hi, Ptr,
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ST->getPointerInfo().getWithOffset(4),
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ST->getOriginalAlign(), MMOFlags, AAInfo);
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@ -578,7 +578,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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// Store the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
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Hi = DAG.getNode(
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ISD::SRL, dl, Value.getValueType(), Value,
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DAG.getConstant(RoundWidth, dl,
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@ -790,7 +790,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
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@ -818,7 +818,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
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@ -1426,7 +1426,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
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unsigned Offset = TypeByteSize*i;
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SDValue Idx = DAG.getMemBasePlusOffset(FIPtr, Offset, dl);
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SDValue Idx = DAG.getMemBasePlusOffset(FIPtr, TypeSize::Fixed(Offset), dl);
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if (Truncate)
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Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
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@ -1487,7 +1487,8 @@ void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
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} else {
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// Advance the pointer so that the loaded byte will contain the sign bit.
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unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
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IntPtr = DAG.getMemBasePlusOffset(StackPtr, ByteOffset, DL);
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IntPtr =
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DAG.getMemBasePlusOffset(StackPtr, TypeSize::Fixed(ByteOffset), DL);
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State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
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ByteOffset);
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}
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@ -2394,7 +2395,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
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SDValue Store1 = DAG.getStore(MemChain, dl, Lo, StackSlot,
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MachinePointerInfo());
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// Store the hi of the constructed double.
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SDValue HiPtr = DAG.getMemBasePlusOffset(StackSlot, 4, dl);
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SDValue HiPtr = DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), dl);
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SDValue Store2 =
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DAG.getStore(MemChain, dl, Hi, HiPtr, MachinePointerInfo());
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MemChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
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@ -2998,7 +2998,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
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// Increment the pointer to the other half.
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unsigned IncrementSize = NVT.getSizeInBits()/8;
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
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Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
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N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
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N->getOriginalAlign(), MMOFlags, AAInfo);
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@ -3022,7 +3022,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
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N->getOriginalAlign(), MMOFlags, AAInfo);
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// Increment the pointer to the other half.
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
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// Load the rest of the low bits.
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
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N->getPointerInfo().getWithOffset(IncrementSize),
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@ -4267,7 +4267,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
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// Increment the pointer to the other half.
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unsigned IncrementSize = NVT.getSizeInBits()/8;
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Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
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Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
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Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
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N->getPointerInfo().getWithOffset(IncrementSize),
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NEVT, N->getOriginalAlign(), MMOFlags, AAInfo);
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@ -4302,7 +4302,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
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N->getOriginalAlign(), MMOFlags, AAInfo);
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// Increment the pointer to the other half.
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Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
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Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
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// Store the lowest ExcessBits bits in the second half.
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Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
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N->getPointerInfo().getWithOffset(IncrementSize),
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@ -175,7 +175,8 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
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// Increment the pointer to the other half.
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unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
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StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
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StackPtr =
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DAG.getMemBasePlusOffset(StackPtr, TypeSize::Fixed(IncrementSize), dl);
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// Load the second half from the stack slot.
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Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr,
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@ -266,7 +267,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
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// Increment the pointer to the other half.
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unsigned IncrementSize = NVT.getSizeInBits() / 8;
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
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Hi = DAG.getLoad(
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NVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(IncrementSize),
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LD->getOriginalAlign(), LD->getMemOperand()->getFlags(), AAInfo);
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@ -481,7 +482,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
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St->getOriginalAlign(), St->getMemOperand()->getFlags(),
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AAInfo);
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Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
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Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
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Hi = DAG.getStore(
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Chain, dl, Hi, Ptr, St->getPointerInfo().getWithOffset(IncrementSize),
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St->getOriginalAlign(), St->getMemOperand()->getFlags(), AAInfo);
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@ -998,7 +998,7 @@ void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT,
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} else {
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MPI = N->getPointerInfo().getWithOffset(IncrementSize);
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// Increment the pointer to the other half.
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Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize);
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Ptr = DAG.getObjectPtrOffset(DL, Ptr, TypeSize::Fixed(IncrementSize));
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}
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}
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@ -1207,7 +1207,8 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
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// Increment the pointer to the other part.
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unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
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StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
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StackPtr =
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DAG.getMemBasePlusOffset(StackPtr, TypeSize::Fixed(IncrementSize), dl);
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// Load the Hi part from the stack slot.
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Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr,
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@ -1510,7 +1511,8 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
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// Increment the pointer to the other part.
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unsigned IncrementSize = LoVT.getSizeInBits() / 8;
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StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
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StackPtr =
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DAG.getMemBasePlusOffset(StackPtr, TypeSize::Fixed(IncrementSize), dl);
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// Load the Hi part from the stack slot.
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Hi = DAG.getLoad(HiVT, dl, Store, StackPtr,
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@ -4990,7 +4992,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
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while (LdWidth > 0) {
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unsigned Increment = NewVTWidth / 8;
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Offset += Increment;
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BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
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BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, TypeSize::Fixed(Increment));
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SDValue L;
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if (LdWidth < NewVTWidth) {
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@ -5107,7 +5109,8 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
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LdChain.push_back(Ops[0].getValue(1));
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unsigned i = 0, Offset = Increment;
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for (i=1; i < NumElts; ++i, Offset += Increment) {
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SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
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SDValue NewBasePtr =
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DAG.getObjectPtrOffset(dl, BasePtr, TypeSize::Fixed(Offset));
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Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
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LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
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LD->getOriginalAlign(), MMOFlags, AAInfo);
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@ -5161,7 +5164,8 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
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Offset += Increment;
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Idx += NumVTElts;
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BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
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BasePtr =
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DAG.getObjectPtrOffset(dl, BasePtr, TypeSize::Fixed(Increment));
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} while (StWidth != 0 && StWidth >= NewVTWidth);
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} else {
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// Cast the vector to the scalar type we can store.
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@ -5178,7 +5182,8 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
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ST->getOriginalAlign(), MMOFlags, AAInfo));
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StWidth -= NewVTWidth;
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Offset += Increment;
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BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
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BasePtr =
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DAG.getObjectPtrOffset(dl, BasePtr, TypeSize::Fixed(Increment));
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} while (StWidth != 0 && StWidth >= NewVTWidth);
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// Restore index back to be relative to the original widen element type.
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Idx = Idx * NewVTWidth / ValEltWidth;
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@ -5219,7 +5224,8 @@ DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
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ST->getOriginalAlign(), MMOFlags, AAInfo));
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unsigned Offset = Increment;
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for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
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SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
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SDValue NewBasePtr =
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DAG.getObjectPtrOffset(dl, BasePtr, TypeSize::Fixed(Offset));
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SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
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DAG.getVectorIdxConstant(0, dl));
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StChain.push_back(DAG.getTruncStore(
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@ -5933,11 +5933,12 @@ static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG,
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return SDValue(nullptr, 0);
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}
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SDValue SelectionDAG::getMemBasePlusOffset(SDValue Base, int64_t Offset,
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SDValue SelectionDAG::getMemBasePlusOffset(SDValue Base, TypeSize Offset,
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const SDLoc &DL,
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const SDNodeFlags Flags) {
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EVT VT = Base.getValueType();
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return getMemBasePlusOffset(Base, getConstant(Offset, DL, VT), DL, Flags);
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return getMemBasePlusOffset(Base, getConstant(Offset.getFixedSize(), DL, VT),
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DL, Flags);
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}
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SDValue SelectionDAG::getMemBasePlusOffset(SDValue Ptr, SDValue Offset,
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@ -6104,7 +6105,8 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
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Value = getMemsetStringVal(VT, dl, DAG, TLI, SubSlice);
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if (Value.getNode()) {
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Store = DAG.getStore(
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Chain, dl, Value, DAG.getMemBasePlusOffset(Dst, DstOff, dl),
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Chain, dl, Value,
|
||||
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
|
||||
DstPtrInfo.getWithOffset(DstOff), Alignment.value(), MMOFlags);
|
||||
OutChains.push_back(Store);
|
||||
}
|
||||
|
|
@ -6125,15 +6127,16 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
|
|||
if (isDereferenceable)
|
||||
SrcMMOFlags |= MachineMemOperand::MODereferenceable;
|
||||
|
||||
Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
|
||||
DAG.getMemBasePlusOffset(Src, SrcOff, dl),
|
||||
SrcPtrInfo.getWithOffset(SrcOff), VT,
|
||||
commonAlignment(*SrcAlign, SrcOff).value(),
|
||||
SrcMMOFlags);
|
||||
Value = DAG.getExtLoad(
|
||||
ISD::EXTLOAD, dl, NVT, Chain,
|
||||
DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl),
|
||||
SrcPtrInfo.getWithOffset(SrcOff), VT,
|
||||
commonAlignment(*SrcAlign, SrcOff).value(), SrcMMOFlags);
|
||||
OutLoadChains.push_back(Value.getValue(1));
|
||||
|
||||
Store = DAG.getTruncStore(
|
||||
Chain, dl, Value, DAG.getMemBasePlusOffset(Dst, DstOff, dl),
|
||||
Chain, dl, Value,
|
||||
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
|
||||
DstPtrInfo.getWithOffset(DstOff), VT, Alignment.value(), MMOFlags);
|
||||
OutStoreChains.push_back(Store);
|
||||
}
|
||||
|
|
@ -6255,7 +6258,8 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
|
|||
SrcMMOFlags |= MachineMemOperand::MODereferenceable;
|
||||
|
||||
Value = DAG.getLoad(
|
||||
VT, dl, Chain, DAG.getMemBasePlusOffset(Src, SrcOff, dl),
|
||||
VT, dl, Chain,
|
||||
DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl),
|
||||
SrcPtrInfo.getWithOffset(SrcOff), SrcAlign->value(), SrcMMOFlags);
|
||||
LoadValues.push_back(Value);
|
||||
LoadChains.push_back(Value.getValue(1));
|
||||
|
|
@ -6269,7 +6273,8 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
|
|||
SDValue Store;
|
||||
|
||||
Store = DAG.getStore(
|
||||
Chain, dl, LoadValues[i], DAG.getMemBasePlusOffset(Dst, DstOff, dl),
|
||||
Chain, dl, LoadValues[i],
|
||||
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
|
||||
DstPtrInfo.getWithOffset(DstOff), Alignment.value(), MMOFlags);
|
||||
OutChains.push_back(Store);
|
||||
DstOff += VTSize;
|
||||
|
|
@ -6368,7 +6373,8 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
|
|||
}
|
||||
assert(Value.getValueType() == VT && "Value with wrong type.");
|
||||
SDValue Store = DAG.getStore(
|
||||
Chain, dl, Value, DAG.getMemBasePlusOffset(Dst, DstOff, dl),
|
||||
Chain, dl, Value,
|
||||
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
|
||||
DstPtrInfo.getWithOffset(DstOff), Alignment.value(),
|
||||
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone);
|
||||
OutChains.push_back(Store);
|
||||
|
|
|
|||
|
|
@ -1843,7 +1843,8 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
|
|||
for (unsigned i = 0; i != NumValues; ++i) {
|
||||
// An aggregate return value cannot wrap around the address space, so
|
||||
// offsets to its parts don't wrap either.
|
||||
SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]);
|
||||
SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr,
|
||||
TypeSize::Fixed(Offsets[i]));
|
||||
|
||||
SDValue Val = RetOp.getValue(RetOp.getResNo() + i);
|
||||
if (MemVTs[i] != ValueVTs[i])
|
||||
|
|
@ -4167,7 +4168,8 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
|||
Root = Chain;
|
||||
ChainI = 0;
|
||||
}
|
||||
SDValue Add = DAG.getMemBasePlusOffset(Ptr, Offsets[i], dl, Flags);
|
||||
SDValue Add =
|
||||
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(Offsets[i]), dl, Flags);
|
||||
SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
|
||||
if (MemVTs[i] != ValueVTs[i])
|
||||
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
|
||||
|
|
|
|||
|
|
@ -3588,7 +3588,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
|
|||
shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
|
||||
SDValue Ptr = Lod->getBasePtr();
|
||||
if (bestOffset != 0)
|
||||
Ptr = DAG.getMemBasePlusOffset(Ptr, bestOffset, dl);
|
||||
Ptr =
|
||||
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(bestOffset), dl);
|
||||
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
|
||||
SDValue NewLoad = DAG.getLoad(
|
||||
newVT, dl, Lod->getChain(), Ptr,
|
||||
|
|
@ -6789,7 +6790,7 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
|
|||
SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
|
||||
LD->getMemOperand()->getFlags(), LD->getAAInfo());
|
||||
|
||||
BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, Stride);
|
||||
BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, TypeSize::Fixed(Stride));
|
||||
|
||||
Vals.push_back(ScalarLoad.getValue(0));
|
||||
LoadChains.push_back(ScalarLoad.getValue(1));
|
||||
|
|
@ -6860,7 +6861,8 @@ SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
|
|||
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
|
||||
DAG.getVectorIdxConstant(Idx, SL));
|
||||
|
||||
SDValue Ptr = DAG.getObjectPtrOffset(SL, BasePtr, Idx * Stride);
|
||||
SDValue Ptr =
|
||||
DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Idx * Stride));
|
||||
|
||||
// This scalar TruncStore may be illegal, but we legalize it later.
|
||||
SDValue Store = DAG.getTruncStore(
|
||||
|
|
@ -6996,7 +6998,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
|
|||
NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
|
||||
LD->getAAInfo());
|
||||
|
||||
Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
|
||||
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
|
||||
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
|
||||
LD->getPointerInfo().getWithOffset(IncrementSize),
|
||||
NewLoadedVT, MinAlign(Alignment, IncrementSize),
|
||||
|
|
@ -7006,7 +7008,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
|
|||
NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
|
||||
LD->getAAInfo());
|
||||
|
||||
Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
|
||||
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
|
||||
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
|
||||
LD->getPointerInfo().getWithOffset(IncrementSize),
|
||||
NewLoadedVT, MinAlign(Alignment, IncrementSize),
|
||||
|
|
@ -7124,8 +7126,8 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
|
|||
"Unaligned store of unknown type.");
|
||||
// Get the half-size VT
|
||||
EVT NewStoredVT = StoreMemVT.getHalfSizedIntegerVT(*DAG.getContext());
|
||||
int NumBits = NewStoredVT.getSizeInBits();
|
||||
int IncrementSize = NumBits / 8;
|
||||
unsigned NumBits = NewStoredVT.getSizeInBits().getFixedSize();
|
||||
unsigned IncrementSize = NumBits / 8;
|
||||
|
||||
// Divide the stored value in two parts.
|
||||
SDValue ShiftAmount = DAG.getConstant(
|
||||
|
|
@ -7140,7 +7142,7 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
|
|||
Ptr, ST->getPointerInfo(), NewStoredVT, Alignment,
|
||||
ST->getMemOperand()->getFlags());
|
||||
|
||||
Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
|
||||
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
|
||||
Alignment = MinAlign(Alignment, IncrementSize);
|
||||
Store2 = DAG.getTruncStore(
|
||||
Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
|
||||
|
|
|
|||
|
|
@ -82,7 +82,8 @@ static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl,
|
|||
unsigned OffsetScaled = 0;
|
||||
while (OffsetScaled < ObjSizeScaled) {
|
||||
if (ObjSizeScaled - OffsetScaled >= 2) {
|
||||
SDValue AddrNode = DAG.getMemBasePlusOffset(Ptr, OffsetScaled * 16, dl);
|
||||
SDValue AddrNode =
|
||||
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(OffsetScaled * 16), dl);
|
||||
SDValue St = DAG.getMemIntrinsicNode(
|
||||
OpCode2, dl, DAG.getVTList(MVT::Other),
|
||||
{Chain, TagSrc, AddrNode},
|
||||
|
|
@ -94,7 +95,8 @@ static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl,
|
|||
}
|
||||
|
||||
if (ObjSizeScaled - OffsetScaled > 0) {
|
||||
SDValue AddrNode = DAG.getMemBasePlusOffset(Ptr, OffsetScaled * 16, dl);
|
||||
SDValue AddrNode =
|
||||
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(OffsetScaled * 16), dl);
|
||||
SDValue St = DAG.getMemIntrinsicNode(
|
||||
OpCode1, dl, DAG.getVTList(MVT::Other),
|
||||
{Chain, TagSrc, AddrNode},
|
||||
|
|
|
|||
|
|
@ -1544,7 +1544,7 @@ SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
|
|||
SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
|
||||
Load->getChain(), BasePtr, SrcValue, LoMemVT,
|
||||
BaseAlign, Load->getMemOperand()->getFlags());
|
||||
SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
|
||||
SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Size));
|
||||
SDValue HiLoad =
|
||||
DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
|
||||
HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
|
||||
|
|
|
|||
|
|
@ -1564,7 +1564,7 @@ SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
|
|||
SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
|
||||
MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
|
||||
|
||||
return DAG.getObjectPtrOffset(SL, BasePtr, Offset);
|
||||
return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Offset));
|
||||
}
|
||||
|
||||
SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
|
||||
|
|
@ -5181,7 +5181,8 @@ SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
|
|||
// private_segment_aperture_base_hi.
|
||||
uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
|
||||
|
||||
SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset);
|
||||
SDValue Ptr =
|
||||
DAG.getObjectPtrOffset(DL, QueuePtr, TypeSize::Fixed(StructOffset));
|
||||
|
||||
// TODO: Use custom target PseudoSourceValue.
|
||||
// TODO: We should use the value from the IR intrinsic call, but it might not
|
||||
|
|
|
|||
|
|
@ -14502,7 +14502,8 @@ static SDValue PerformSplittingToNarrowingStores(StoreSDNode *St,
|
|||
SmallVector<SDValue, 4> Stores;
|
||||
for (unsigned i = 0; i < FromVT.getVectorNumElements() / NumElements; i++) {
|
||||
unsigned NewOffset = i * NumElements * ToEltVT.getSizeInBits() / 8;
|
||||
SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset);
|
||||
SDValue NewPtr =
|
||||
DAG.getObjectPtrOffset(DL, BasePtr, TypeSize::Fixed(NewOffset));
|
||||
|
||||
SDValue Extract =
|
||||
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewFromVT, Trunc.getOperand(0),
|
||||
|
|
@ -15312,7 +15313,8 @@ static SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
|
|||
SmallVector<SDValue, 4> Chains;
|
||||
for (unsigned i = 0; i < FromVT.getVectorNumElements() / NumElements; i++) {
|
||||
unsigned NewOffset = (i * NewFromVT.getSizeInBits()) / 8;
|
||||
SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset);
|
||||
SDValue NewPtr =
|
||||
DAG.getObjectPtrOffset(DL, BasePtr, TypeSize::Fixed(NewOffset));
|
||||
|
||||
SDValue NewLoad =
|
||||
DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset,
|
||||
|
|
|
|||
|
|
@ -2910,8 +2910,10 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
|
|||
? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
|
||||
DAG.getConstant(NeedAlign, dl, MVT::i32))
|
||||
: BO.first;
|
||||
SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
|
||||
SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);
|
||||
SDValue Base0 =
|
||||
DAG.getMemBasePlusOffset(BaseNoOff, TypeSize::Fixed(BO.second), dl);
|
||||
SDValue Base1 = DAG.getMemBasePlusOffset(
|
||||
BaseNoOff, TypeSize::Fixed(BO.second + LoadLen), dl);
|
||||
|
||||
MachineMemOperand *WideMMO = nullptr;
|
||||
if (MachineMemOperand *MMO = LN->getMemOperand()) {
|
||||
|
|
|
|||
|
|
@ -1659,7 +1659,7 @@ HexagonTargetLowering::SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const {
|
|||
MVT SingleTy = typeSplit(MemTy).first;
|
||||
SDValue Chain = BN->getChain();
|
||||
SDValue Base0 = BN->getBasePtr();
|
||||
SDValue Base1 = DAG.getMemBasePlusOffset(Base0, HwLen, dl);
|
||||
SDValue Base1 = DAG.getMemBasePlusOffset(Base0, TypeSize::Fixed(HwLen), dl);
|
||||
|
||||
MachineMemOperand *MOp0 = nullptr, *MOp1 = nullptr;
|
||||
if (MachineMemOperand *MMO = BN->getMemOperand()) {
|
||||
|
|
|
|||
|
|
@ -7107,10 +7107,10 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
|
|||
// to extracting the value from the register directly, and elide the
|
||||
// stores when the arguments address is not taken, but that will need to
|
||||
// be future work.
|
||||
SDValue Store =
|
||||
DAG.getStore(CopyFrom.getValue(1), dl, CopyFrom,
|
||||
DAG.getObjectPtrOffset(dl, FIN, Offset),
|
||||
MachinePointerInfo::getFixedStack(MF, FI, Offset));
|
||||
SDValue Store = DAG.getStore(
|
||||
CopyFrom.getValue(1), dl, CopyFrom,
|
||||
DAG.getObjectPtrOffset(dl, FIN, TypeSize::Fixed(Offset)),
|
||||
MachinePointerInfo::getFixedStack(MF, FI, Offset));
|
||||
|
||||
MemOps.push_back(Store);
|
||||
};
|
||||
|
|
@ -7307,11 +7307,12 @@ SDValue PPCTargetLowering::LowerCall_AIX(
|
|||
}
|
||||
|
||||
auto GetLoad = [&](EVT VT, unsigned LoadOffset) {
|
||||
return DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain,
|
||||
(LoadOffset != 0)
|
||||
? DAG.getObjectPtrOffset(dl, Arg, LoadOffset)
|
||||
: Arg,
|
||||
MachinePointerInfo(), VT);
|
||||
return DAG.getExtLoad(
|
||||
ISD::ZEXTLOAD, dl, PtrVT, Chain,
|
||||
(LoadOffset != 0)
|
||||
? DAG.getObjectPtrOffset(dl, Arg, TypeSize::Fixed(LoadOffset))
|
||||
: Arg,
|
||||
MachinePointerInfo(), VT);
|
||||
};
|
||||
|
||||
unsigned LoadOffset = 0;
|
||||
|
|
@ -7341,9 +7342,11 @@ SDValue PPCTargetLowering::LowerCall_AIX(
|
|||
// Only memcpy the bytes that don't pass in register.
|
||||
MemcpyFlags.setByValSize(ByValSize - LoadOffset);
|
||||
Chain = CallSeqStart = createMemcpyOutsideCallSeq(
|
||||
(LoadOffset != 0) ? DAG.getObjectPtrOffset(dl, Arg, LoadOffset)
|
||||
: Arg,
|
||||
DAG.getObjectPtrOffset(dl, StackPtr, ByValVA.getLocMemOffset()),
|
||||
(LoadOffset != 0)
|
||||
? DAG.getObjectPtrOffset(dl, Arg, TypeSize::Fixed(LoadOffset))
|
||||
: Arg,
|
||||
DAG.getObjectPtrOffset(dl, StackPtr,
|
||||
TypeSize::Fixed(ByValVA.getLocMemOffset())),
|
||||
CallSeqStart, MemcpyFlags, DAG, dl);
|
||||
continue;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13312,7 +13312,8 @@ static SDValue lowerShuffleAsBroadcast(const SDLoc &DL, MVT VT, SDValue V1,
|
|||
MVT SVT = VT.getScalarType();
|
||||
unsigned Offset = BroadcastIdx * SVT.getStoreSize();
|
||||
assert((int)(Offset * 8) == BitOffset && "Unexpected bit-offset");
|
||||
SDValue NewAddr = DAG.getMemBasePlusOffset(BaseAddr, Offset, DL);
|
||||
SDValue NewAddr =
|
||||
DAG.getMemBasePlusOffset(BaseAddr, TypeSize::Fixed(Offset), DL);
|
||||
|
||||
// Directly form VBROADCAST_LOAD if we're using VBROADCAST opcode rather
|
||||
// than MOVDDUP.
|
||||
|
|
@ -19963,7 +19964,8 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
|
|||
MachinePointerInfo MPI =
|
||||
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI);
|
||||
if (SrcVT == MVT::i32) {
|
||||
SDValue OffsetSlot = DAG.getMemBasePlusOffset(StackSlot, 4, dl);
|
||||
SDValue OffsetSlot =
|
||||
DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), dl);
|
||||
SDValue Store1 =
|
||||
DAG.getStore(Chain, dl, Src, StackSlot, MPI, 8 /*Align*/);
|
||||
SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
|
||||
|
|
@ -23487,7 +23489,8 @@ static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
|
|||
std::tie(Value0, Value1) = splitVector(StoredVal, DAG, DL);
|
||||
unsigned HalfOffset = Value0.getValueType().getStoreSize();
|
||||
SDValue Ptr0 = Store->getBasePtr();
|
||||
SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, HalfOffset, DL);
|
||||
SDValue Ptr1 =
|
||||
DAG.getMemBasePlusOffset(Ptr0, TypeSize::Fixed(HalfOffset), DL);
|
||||
SDValue Ch0 =
|
||||
DAG.getStore(Store->getChain(), DL, Value0, Ptr0, Store->getPointerInfo(),
|
||||
Store->getOriginalAlign(),
|
||||
|
|
@ -23522,7 +23525,8 @@ static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT,
|
|||
SmallVector<SDValue, 4> Stores;
|
||||
for (unsigned i = 0; i != NumElems; ++i) {
|
||||
unsigned Offset = i * ScalarSize;
|
||||
SDValue Ptr = DAG.getMemBasePlusOffset(Store->getBasePtr(), Offset, DL);
|
||||
SDValue Ptr = DAG.getMemBasePlusOffset(Store->getBasePtr(),
|
||||
TypeSize::Fixed(Offset), DL);
|
||||
SDValue Scl = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreSVT, StoredVal,
|
||||
DAG.getIntPtrConstant(i, DL));
|
||||
SDValue Ch = DAG.getStore(Store->getChain(), DL, Scl, Ptr,
|
||||
|
|
@ -23910,7 +23914,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
|||
MemOps.push_back(Store);
|
||||
|
||||
// Store fp_offset
|
||||
FIN = DAG.getMemBasePlusOffset(FIN, 4, DL);
|
||||
FIN = DAG.getMemBasePlusOffset(FIN, TypeSize::Fixed(4), DL);
|
||||
Store = DAG.getStore(
|
||||
Op.getOperand(0), DL,
|
||||
DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL, MVT::i32), FIN,
|
||||
|
|
@ -36169,7 +36173,8 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
|
|||
LN->isSimple()) {
|
||||
unsigned Offset = ShiftAmt / 8;
|
||||
SDVTList Tys = DAG.getVTList(VT, MVT::Other);
|
||||
SDValue Ptr = DAG.getMemBasePlusOffset(LN->getBasePtr(), Offset, DL);
|
||||
SDValue Ptr = DAG.getMemBasePlusOffset(LN->getBasePtr(),
|
||||
TypeSize::Fixed(Offset), DL);
|
||||
SDValue Ops[] = { LN->getChain(), Ptr };
|
||||
SDValue BcastLd = DAG.getMemIntrinsicNode(
|
||||
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, MVT::i16,
|
||||
|
|
@ -43898,7 +43903,8 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
|
|||
|
||||
unsigned HalfOffset = 16;
|
||||
SDValue Ptr1 = Ld->getBasePtr();
|
||||
SDValue Ptr2 = DAG.getMemBasePlusOffset(Ptr1, HalfOffset, dl);
|
||||
SDValue Ptr2 =
|
||||
DAG.getMemBasePlusOffset(Ptr1, TypeSize::Fixed(HalfOffset), dl);
|
||||
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
|
||||
NumElems / 2);
|
||||
SDValue Load1 =
|
||||
|
|
@ -44000,7 +44006,8 @@ static bool getParamsForOneTrueMaskedElt(MaskedLoadStoreSDNode *MaskedOp,
|
|||
Addr = MaskedOp->getBasePtr();
|
||||
if (TrueMaskElt != 0) {
|
||||
unsigned Offset = TrueMaskElt * EltVT.getStoreSize();
|
||||
Addr = DAG.getMemBasePlusOffset(Addr, Offset, SDLoc(MaskedOp));
|
||||
Addr = DAG.getMemBasePlusOffset(Addr, TypeSize::Fixed(Offset),
|
||||
SDLoc(MaskedOp));
|
||||
}
|
||||
|
||||
Index = DAG.getIntPtrConstant(TrueMaskElt, SDLoc(MaskedOp));
|
||||
|
|
@ -44265,7 +44272,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
|
|||
Hi = combinevXi1ConstantToInteger(Hi, DAG);
|
||||
|
||||
SDValue Ptr0 = St->getBasePtr();
|
||||
SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, 4, dl);
|
||||
SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, TypeSize::Fixed(4), dl);
|
||||
|
||||
SDValue Ch0 =
|
||||
DAG.getStore(St->getChain(), dl, Lo, Ptr0, St->getPointerInfo(),
|
||||
|
|
|
|||
Loading…
Reference in New Issue