forked from OSchip/llvm-project
[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1.
This extends the existing support for shufflevector to handle cases like <2 x float>, which we can implement by concating the vectors and using a TBL1. Differential Revision: https://reviews.llvm.org/D58684 llvm-svn: 355104
This commit is contained in:
Amara Emerson
parent
5d4d168c3c
commit
85c3afd7f6
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@ -82,6 +82,8 @@ private:
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unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
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MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitVectorConcat(unsigned Op1, unsigned Op2,
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MachineIRBuilder &MIRBuilder) const;
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ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
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@ -1965,6 +1967,98 @@ MachineInstr *AArch64InstructionSelector::emitLoadFromConstantPool(
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return &*Load;
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}
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/// Return an <Opcode, SubregIndex> pair to do an vector elt insert of a given
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/// size and RB.
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static std::pair<unsigned, unsigned>
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getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
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unsigned Opc, SubregIdx;
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if (RB.getID() == AArch64::GPRRegBankID) {
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if (EltSize == 32) {
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Opc = AArch64::INSvi32gpr;
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SubregIdx = AArch64::ssub;
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} else if (EltSize == 64) {
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Opc = AArch64::INSvi64gpr;
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SubregIdx = AArch64::dsub;
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} else {
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llvm_unreachable("invalid elt size!");
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}
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} else {
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if (EltSize == 8) {
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Opc = AArch64::INSvi8lane;
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SubregIdx = AArch64::bsub;
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} else if (EltSize == 16) {
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Opc = AArch64::INSvi16lane;
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SubregIdx = AArch64::hsub;
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} else if (EltSize == 32) {
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Opc = AArch64::INSvi32lane;
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SubregIdx = AArch64::ssub;
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} else if (EltSize == 64) {
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Opc = AArch64::INSvi64lane;
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SubregIdx = AArch64::dsub;
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} else {
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llvm_unreachable("invalid elt size!");
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}
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}
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return std::make_pair(Opc, SubregIdx);
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}
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MachineInstr *AArch64InstructionSelector::emitVectorConcat(
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unsigned Op1, unsigned Op2, MachineIRBuilder &MIRBuilder) const {
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// We implement a vector concat by:
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// 1. Use scalar_to_vector to insert the lower vector into the larger dest
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// 2. Insert the upper vector into the destination's upper element
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// TODO: some of this code is common with G_BUILD_VECTOR handling.
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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const LLT Op1Ty = MRI.getType(Op1);
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const LLT Op2Ty = MRI.getType(Op2);
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if (Op1Ty != Op2Ty) {
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LLVM_DEBUG(dbgs() << "Could not do vector concat of differing vector tys");
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return nullptr;
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}
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assert(Op1Ty.isVector() && "Expected a vector for vector concat");
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if (Op1Ty.getSizeInBits() >= 128) {
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LLVM_DEBUG(dbgs() << "Vector concat not supported for full size vectors");
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return nullptr;
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}
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// At the moment we just support 64 bit vector concats.
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if (Op1Ty.getSizeInBits() != 64) {
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LLVM_DEBUG(dbgs() << "Vector concat supported for 64b vectors");
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return nullptr;
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}
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const LLT ScalarTy = LLT::scalar(Op1Ty.getSizeInBits());
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const LLT &DstTy = LLT::vector(2, ScalarTy);
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const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI);
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const TargetRegisterClass *DstRC =
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getMinClassForRegBank(FPRBank, Op1Ty.getSizeInBits() * 2);
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MachineInstr *WidenedOp1 = emitScalarToVector(DstTy, DstRC, Op1, MIRBuilder);
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MachineInstr *WidenedOp2 = emitScalarToVector(DstTy, DstRC, Op2, MIRBuilder);
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if (!WidenedOp1 || !WidenedOp2) {
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LLVM_DEBUG(dbgs() << "Could not emit a vector from scalar value");
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return nullptr;
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}
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// Now do the insert of the upper element.
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unsigned InsertOpc, InsSubRegIdx;
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std::tie(InsertOpc, InsSubRegIdx) =
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getInsertVecEltOpInfo(FPRBank, ScalarTy.getSizeInBits());
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auto InsElt =
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MIRBuilder
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.buildInstr(InsertOpc, {DstRC}, {WidenedOp1->getOperand(0).getReg()})
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.addImm(1) /* Lane index */
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.addUse(WidenedOp2->getOperand(0).getReg())
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.addImm(0);
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constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI);
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return &*InsElt;
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}
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bool AArch64InstructionSelector::selectShuffleVector(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
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@ -2002,21 +2096,37 @@ bool AArch64InstructionSelector::selectShuffleVector(
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}
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}
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if (DstTy.getSizeInBits() != 128) {
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assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");
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// This case can be done with TBL1.
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return false;
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}
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MachineIRBuilder MIRBuilder(I);
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// Use a constant pool to load the index vector for TBL.
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Constant *CPVal = ConstantVector::get(CstIdxs);
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MachineIRBuilder MIRBuilder(I);
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MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIRBuilder);
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if (!IndexLoad) {
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LLVM_DEBUG(dbgs() << "Could not load from a constant pool");
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return false;
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}
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if (DstTy.getSizeInBits() != 128) {
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assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");
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// This case can be done with TBL1.
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MachineInstr *Concat = emitVectorConcat(Src1Reg, Src2Reg, MIRBuilder);
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if (!Concat) {
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LLVM_DEBUG(dbgs() << "Could not do vector concat for tbl1");
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return false;
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}
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auto TBL1 = MIRBuilder.buildInstr(
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AArch64::TBLv16i8One, {&AArch64::FPR128RegClass},
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{Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
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constrainSelectedInstRegOperands(*TBL1, TII, TRI, RBI);
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auto Copy = BuildMI(*I.getParent(), I, I.getDebugLoc(),
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TII.get(TargetOpcode::COPY), I.getOperand(0).getReg())
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.addUse(TBL1->getOperand(0).getReg(), 0, AArch64::dsub);
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RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);
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I.eraseFromParent();
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return true;
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}
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// For TBL2 we need to emit a REG_SEQUENCE to tie together two consecutive
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// Q registers for regalloc.
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auto RegSeq = MIRBuilder
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@ -2048,26 +2158,8 @@ bool AArch64InstructionSelector::selectBuildVector(
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const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
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unsigned Opc;
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unsigned SubregIdx;
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if (RB.getID() == AArch64::GPRRegBankID) {
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if (EltSize == 32) {
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Opc = AArch64::INSvi32gpr;
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SubregIdx = AArch64::ssub;
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} else {
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Opc = AArch64::INSvi64gpr;
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SubregIdx = AArch64::dsub;
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}
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} else {
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if (EltSize == 16) {
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Opc = AArch64::INSvi16lane;
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SubregIdx = AArch64::hsub;
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} else if (EltSize == 32) {
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Opc = AArch64::INSvi32lane;
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SubregIdx = AArch64::ssub;
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} else {
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Opc = AArch64::INSvi64lane;
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SubregIdx = AArch64::dsub;
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}
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}
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std::tie(Opc, SubregIdx) = getInsertVecEltOpInfo(RB, EltSize);
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MachineIRBuilder MIRBuilder(I);
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@ -1,11 +1,17 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# WARNING: update_mir_test_checks.py does not include the constant pools output,
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# so this test requires manual fixing up after running the script.
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# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
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--- |
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; ModuleID = 'shufflevec-only-legal.ll'
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source_filename = "shufflevec-only-legal.ll"
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define <2 x float> @shuffle_v2f32(<2 x float> %a, <2 x float> %b) {
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%shuf = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 0>
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ret <2 x float> %shuf
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}
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define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
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%shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0>
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ret <4 x i32> %shuf
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@ -21,6 +27,45 @@
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ret <2 x i64> %shuf
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}
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...
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---
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name: shuffle_v2f32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0, $d1
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; CHECK-LABEL: name: shuffle_v2f32
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; CHECK: constants:
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; CHECK: - id: 0
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; CHECK: value: '<8 x i8> <i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
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; CHECK: alignment: 8
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
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; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[LDRQui]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
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; CHECK: $d0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%4:gpr(s32) = G_CONSTANT i32 1
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%5:gpr(s32) = G_CONSTANT i32 0
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%3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32)
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%2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, %3(<2 x s32>)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: shuffle_v4i32
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@ -28,14 +73,6 @@ alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $q1
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@ -71,15 +108,6 @@ alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $q1
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@ -116,12 +144,6 @@ alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $q1
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