forked from OSchip/llvm-project
[AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector
NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT. Also better code-reuse, etc., etc. Differential Revision: https://reviews.llvm.org/D59323 llvm-svn: 356107
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@ -2383,28 +2383,24 @@ bool AArch64InstructionSelector::selectBuildVector(
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// If DstTy's size in bits is less than 128, then emit a subregister copy
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// from DstVec to the last register we've defined.
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if (DstSize < 128) {
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unsigned SubReg = 0;
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// Helper lambda to decide on a register class and subregister for the
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// subregister copy.
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auto GetRegInfoForCopy = [&SubReg,
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&DstSize]() -> const TargetRegisterClass * {
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switch (DstSize) {
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default:
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LLVM_DEBUG(dbgs() << "Unknown destination size (" << DstSize << ")\n");
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return nullptr;
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case 32:
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SubReg = AArch64::ssub;
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return &AArch64::FPR32RegClass;
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case 64:
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SubReg = AArch64::dsub;
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return &AArch64::FPR64RegClass;
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}
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};
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const TargetRegisterClass *RC = GetRegInfoForCopy();
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// Force this to be FPR using the destination vector.
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const TargetRegisterClass *RC =
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getMinClassForRegBank(*RBI.getRegBank(DstVec, MRI, TRI), DstSize);
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if (!RC)
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return false;
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if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
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LLVM_DEBUG(dbgs() << "Unsupported register class!\n");
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return false;
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}
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unsigned SubReg = 0;
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if (!getSubRegForClass(RC, TRI, SubReg))
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return false;
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if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) {
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LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << DstSize
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<< "\n");
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return false;
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}
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unsigned Reg = MRI.createVirtualRegister(RC);
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unsigned DstReg = I.getOperand(0).getReg();
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