[AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector

NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT.

Also better code-reuse, etc., etc.

Differential Revision: https://reviews.llvm.org/D59323

llvm-svn: 356107
This commit is contained in:
Jessica Paquette 2019-03-13 23:29:54 +00:00
parent 16d67a3e32
commit 85ace6269f
1 changed files with 16 additions and 20 deletions

View File

@ -2383,28 +2383,24 @@ bool AArch64InstructionSelector::selectBuildVector(
// If DstTy's size in bits is less than 128, then emit a subregister copy
// from DstVec to the last register we've defined.
if (DstSize < 128) {
unsigned SubReg = 0;
// Helper lambda to decide on a register class and subregister for the
// subregister copy.
auto GetRegInfoForCopy = [&SubReg,
&DstSize]() -> const TargetRegisterClass * {
switch (DstSize) {
default:
LLVM_DEBUG(dbgs() << "Unknown destination size (" << DstSize << ")\n");
return nullptr;
case 32:
SubReg = AArch64::ssub;
return &AArch64::FPR32RegClass;
case 64:
SubReg = AArch64::dsub;
return &AArch64::FPR64RegClass;
}
};
const TargetRegisterClass *RC = GetRegInfoForCopy();
// Force this to be FPR using the destination vector.
const TargetRegisterClass *RC =
getMinClassForRegBank(*RBI.getRegBank(DstVec, MRI, TRI), DstSize);
if (!RC)
return false;
if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
LLVM_DEBUG(dbgs() << "Unsupported register class!\n");
return false;
}
unsigned SubReg = 0;
if (!getSubRegForClass(RC, TRI, SubReg))
return false;
if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) {
LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << DstSize
<< "\n");
return false;
}
unsigned Reg = MRI.createVirtualRegister(RC);
unsigned DstReg = I.getOperand(0).getReg();