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[mips][microMIPSr6] Implement SEB and SEH instructions 

Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
This commit is contained in:
Zoran Jovanovic 2015-05-27 15:39:47 +00:00
parent 2e4be0ad03
commit 85a53a1ed5
5 changed files with 28 additions and 2 deletions
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14
llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
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@ -71,6 +71,20 @@ class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
let Inst{15-0} = imm16; let Inst{15-0} = imm16;
} }
class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm> {
bits<5> rd;
bits<5> rt;
bits<32> Inst;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rd;
let Inst{20-16} = rt;
let Inst{15-6} = funct;
let Inst{5-0} = 0b111100;
}
class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst { class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
bits<5> rt; bits<5> rt;
bits<19> imm; bits<19> imm;

6
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -54,6 +54,8 @@ class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>; class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>; class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>; class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>; class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
@ -204,6 +206,8 @@ class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>; class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MMR6Arch<instr_asm> { : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt); dag OutOperandList = (outs GPROpnd:$rt);
@ -312,6 +316,8 @@ def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6; def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6; def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,

4
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -1410,9 +1410,9 @@ def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
} }
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2; SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2; SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
/// Count Leading /// Count Leading

4
llvm/test/MC/Disassembler/Mips/micromips32r6.txt
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@ -93,3 +93,7 @@
0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234 0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4
0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4

2
llvm/test/MC/Mips/micromips32r6/valid.s
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@ -39,6 +39,8 @@
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2] ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90] sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]