diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index ba159007f03b..92b0c964557c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -3068,12 +3068,22 @@ def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr  R8 :$src1, R8 :$src1)>;
 def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>;
 def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>;
 
-// (or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
+// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
 def : Pat<(or (srl R32:$src1, CL:$amt),
               (shl R32:$src2, (sub 32, CL:$amt))),
           (SHRD32rrCL R32:$src1, R32:$src2)>;
 
-// (or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
+// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
 def : Pat<(or (shl R32:$src1, CL:$amt),
               (srl R32:$src2, (sub 32, CL:$amt))),
           (SHLD32rrCL R32:$src1, R32:$src2)>;
+
+// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
+def : Pat<(or (srl R16:$src1, CL:$amt),
+              (shl R16:$src2, (sub 16, CL:$amt))),
+          (SHRD16rrCL R16:$src1, R16:$src2)>;
+
+// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
+def : Pat<(or (shl R16:$src1, CL:$amt),
+              (srl R16:$src2, (sub 16, CL:$amt))),
+          (SHLD16rrCL R16:$src1, R16:$src2)>;
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 4af0b06c0066..a484b9dac937 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -48,7 +48,7 @@ namespace {
   cl::opt<bool, true> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden,
                       cl::desc("Enable DAG-to-DAG isel for X86"),
                       cl::location(X86DAGIsel),
-                      cl::init(false));
+                      cl::init(true));
   
   // FIXME: This should eventually be handled with target triples and
   // subtarget support!