forked from OSchip/llvm-project
[X86] Fix fptoui conversions
This fixes two issues in x86 fptoui lowering. 1) Makes conversions from f80 go through the right path on AVX-512. 2) Implements an inline sequence for fptoui i64 instead of a library call. This improves performance by 6X on SSE3+ and 3X otherwise. Incidentally, it also removes the use of ftol2 for fptoui, which was wrong to begin with, as ftol2 converts to a signed i64, producing wrong results for values >= 2^63. Patch by: mitch.l.bodart@intel.com Differential Revision: http://reviews.llvm.org/D11316 llvm-svn: 245924
This commit is contained in:
Michael Kuperstein
parent
2c8f9c2c23
commit
8515893be8
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@ -114,13 +114,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
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setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
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setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
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// The _ftol2 runtime function has an unusual calling conv, which
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// is modeled by a special pseudo-instruction.
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setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
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setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
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setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
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setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
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}
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if (Subtarget->isTargetDarwin()) {
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@ -228,8 +221,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
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if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
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// FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
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setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
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} else {
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
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}
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} else if (!Subtarget->useSoftFloat()) {
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// Since AVX is a superset of SSE3, only check for SSE here.
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if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
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@ -238,14 +237,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// the optimal thing for SSE vs. the default expansion in the legalizer.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
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else
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// With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
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// With SSE3 we can use fisttpll to convert to a signed i64; without
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// SSE, we're stuck with a fistpll.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
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}
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if (isTargetFTOL()) {
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// Use the _ftol2 runtime function, which has a pseudo-instruction
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// to handle its weird calling convention.
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setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
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}
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@ -1330,13 +1326,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::FMA, MVT::v8f64, Legal);
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setOperationAction(ISD::FMA, MVT::v16f32, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
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// FIXME: [US]INT_TO_FP are not legal for f80.
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
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}
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@ -12334,15 +12327,45 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
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DAG.getIntPtrConstant(0, dl));
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}
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// If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
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// is legal, or has an f16 source (which needs to be promoted to f32),
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// just return an <SDValue(), SDValue()> pair.
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// Otherwise it is assumed to be a conversion from one of f32, f64 or f80
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// to i16, i32 or i64, and we lower it to a legal sequence.
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// If lowered to the final integer result we return a <result, SDValue()> pair.
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// Otherwise we lower it to a sequence ending with a FIST, return a
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// <FIST, StackSlot> pair, and the caller is responsible for loading
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// the final integer result from StackSlot.
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std::pair<SDValue,SDValue>
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X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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bool IsSigned, bool IsReplace) const {
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X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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bool IsSigned, bool IsReplace) const {
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SDLoc DL(Op);
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EVT DstTy = Op.getValueType();
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EVT TheVT = Op.getOperand(0).getValueType();
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auto PtrVT = getPointerTy(DAG.getDataLayout());
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if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
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if (TheVT == MVT::f16)
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// We need to promote the f16 to f32 before using the lowering
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// in this routine.
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return std::make_pair(SDValue(), SDValue());
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assert((TheVT == MVT::f32 ||
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TheVT == MVT::f64 ||
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TheVT == MVT::f80) &&
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"Unexpected FP operand type in FP_TO_INTHelper");
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// If using FIST to compute an unsigned i64, we'll need some fixup
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// to handle values above the maximum signed i64. A FIST is always
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// used for the 32-bit subtarget, but also for f80 on a 64-bit target.
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bool UnsignedFixup = !IsSigned &&
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DstTy == MVT::i64 &&
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(!Subtarget->is64Bit() ||
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!isScalarFPTypeInSSEReg(TheVT));
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if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
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// Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
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// The low 32 bits of the fist result will have the correct uint32 result.
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assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
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DstTy = MVT::i64;
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}
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@ -12360,27 +12383,72 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
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return std::make_pair(SDValue(), SDValue());
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// We lower FP->int64 either into FISTP64 followed by a load from a temporary
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// stack slot, or into the FTOL runtime function.
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// We lower FP->int64 into FISTP64 followed by a load from a temporary
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// stack slot.
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MachineFunction &MF = DAG.getMachineFunction();
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unsigned MemSize = DstTy.getSizeInBits()/8;
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int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
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SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
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unsigned Opc;
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if (!IsSigned && isIntegerTypeFTOL(DstTy))
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Opc = X86ISD::WIN_FTOL;
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else
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switch (DstTy.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
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case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
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case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
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case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
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}
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switch (DstTy.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
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case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
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case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
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case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
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}
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SDValue Chain = DAG.getEntryNode();
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SDValue Value = Op.getOperand(0);
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EVT TheVT = Op.getOperand(0).getValueType();
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SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
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if (UnsignedFixup) {
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//
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// Conversion to unsigned i64 is implemented with a select,
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// depending on whether the source value fits in the range
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// of a signed i64. Let Thresh be the FP equivalent of
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// 0x8000000000000000ULL.
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//
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// Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
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// FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
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// Fist-to-mem64 FistSrc
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// Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
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// to XOR'ing the high 32 bits with Adjust.
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//
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// Being a power of 2, Thresh is exactly representable in all FP formats.
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// For X87 we'd like to use the smallest FP type for this constant, but
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// for DAG type consistency we have to match the FP operand type.
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APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
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APFloat::opStatus Status = APFloat::opOK;
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bool LosesInfo = false;
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if (TheVT == MVT::f64)
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// The rounding mode is irrelevant as the conversion should be exact.
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Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
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&LosesInfo);
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else if (TheVT == MVT::f80)
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Status = Thresh.convert(APFloat::x87DoubleExtended,
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APFloat::rmNearestTiesToEven, &LosesInfo);
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assert(Status == APFloat::opOK && !LosesInfo &&
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"FP conversion should have been exact");
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SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
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SDValue Cmp = DAG.getSetCC(DL,
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getSetCCResultType(DAG.getDataLayout(),
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*DAG.getContext(), TheVT),
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Value, ThreshVal, ISD::SETLT);
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Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
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DAG.getConstant(0, DL, MVT::i32),
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DAG.getConstant(0x80000000, DL, MVT::i32));
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SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
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Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
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*DAG.getContext(), TheVT),
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Value, ThreshVal, ISD::SETLT);
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Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
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}
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// FIXME This causes a redundant load/store if the SSE-class value is already
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// in memory, such as if it is on the callstack.
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if (isScalarFPTypeInSSEReg(TheVT)) {
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@ -12406,25 +12474,49 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
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MachineMemOperand::MOStore, MemSize, MemSize);
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if (Opc != X86ISD::WIN_FTOL) {
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if (UnsignedFixup) {
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// Insert the FIST, load its result as two i32's,
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// and XOR the high i32 with Adjust.
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SDValue FistOps[] = { Chain, Value, StackSlot };
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SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
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FistOps, DstTy, MMO);
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SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
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MachinePointerInfo(),
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false, false, false, 0);
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SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
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DAG.getConstant(4, DL, PtrVT));
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SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
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MachinePointerInfo(),
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false, false, false, 0);
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High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
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if (Subtarget->is64Bit()) {
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// Join High32 and Low32 into a 64-bit result.
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// (High32 << 32) | Low32
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Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
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High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
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High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
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DAG.getConstant(32, DL, MVT::i8));
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SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
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return std::make_pair(Result, SDValue());
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}
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SDValue ResultOps[] = { Low32, High32 };
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SDValue pair = IsReplace
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? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
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: DAG.getMergeValues(ResultOps, DL);
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return std::make_pair(pair, SDValue());
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} else {
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// Build the FP_TO_INT*_IN_MEM
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SDValue Ops[] = { Chain, Value, StackSlot };
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SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
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Ops, DstTy, MMO);
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return std::make_pair(FIST, StackSlot);
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} else {
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SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
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DAG.getVTList(MVT::Other, MVT::Glue),
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Chain, Value);
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SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
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MVT::i32, ftol.getValue(1));
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SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
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MVT::i32, eax.getValue(2));
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SDValue Ops[] = { eax, edx };
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SDValue pair = IsReplace
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? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
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: DAG.getMergeValues(Ops, DL);
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return std::make_pair(pair, SDValue());
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}
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}
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@ -12688,7 +12780,8 @@ SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
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/*IsSigned=*/ true, /*IsReplace=*/ false);
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SDValue FIST = Vals.first, StackSlot = Vals.second;
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// If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
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if (!FIST.getNode()) return Op;
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if (!FIST.getNode())
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return Op;
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if (StackSlot.getNode())
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// Load the result.
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@ -12705,7 +12798,9 @@ SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
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std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
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/*IsSigned=*/ false, /*IsReplace=*/ false);
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SDValue FIST = Vals.first, StackSlot = Vals.second;
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assert(FIST.getNode() && "Unexpected failure");
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// If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
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if (!FIST.getNode())
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return Op;
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if (StackSlot.getNode())
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// Load the result.
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@ -18885,17 +18980,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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return;
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}
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case ISD::FP_TO_SINT:
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// FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
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// (FP_TO_SINT (load f16)) to FP_TO_INT*.
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if (N->getOperand(0).getValueType() == MVT::f16)
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break;
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// fallthrough
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case ISD::FP_TO_UINT: {
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bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
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if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
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return;
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std::pair<SDValue,SDValue> Vals =
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FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
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SDValue FIST = Vals.first, StackSlot = Vals.second;
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@ -26507,10 +26594,6 @@ int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
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return -1;
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}
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bool X86TargetLowering::isTargetFTOL() const {
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return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
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}
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bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
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// Integer division on x86 is expensive. However, when aggressively optimizing
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// for code size, we prefer to use a div instruction, as it is usually smaller
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@ -856,15 +856,6 @@ namespace llvm {
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(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
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}
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/// Return true if the target uses the MSVC _ftol2 routine for fptoui.
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bool isTargetFTOL() const;
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/// Return true if the MSVC _ftol2 routine should be used for fptoui to the
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/// given type.
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bool isIntegerTypeFTOL(EVT VT) const {
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return isTargetFTOL() && VT == MVT::i64;
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}
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/// \brief Returns true if it is beneficial to convert a load of a constant
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/// to just the constant itself.
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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@ -30,5 +30,5 @@ define <8 x float> @foo(<8 x float> %y, i64* %p, double %x) {
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; CHECK: foo
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; CHECK-NOT: vzeroupper
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; CHECK: _ftol2
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; CHECK: {{cvtt|fist}}
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; CHECK: ret
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@ -0,0 +1,135 @@
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; Check that scalar FP conversions to signed and unsigned int64 are using
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; reasonable sequences, across platforms and target switches.
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;
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; The signed case is straight forward, and the tests here basically
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; ensure successful compilation (f80 with avx512 was broken at one point).
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;
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; For the unsigned case there are many possible sequences, so to avoid
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; a fragile test we just check for the presence of a few key instructions.
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; AVX512 on Intel64 can use vcvtts[ds]2usi directly for float and double.
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; Otherwise the sequence will involve an FP subtract (fsub, subss or subsd),
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; and a truncating conversion (cvtts[ds]2si, fisttp, or fnstcw+fist). When
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; both a subtract and fnstcw are needed, they can occur in either order.
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;
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; The interesting subtargets are AVX512F (vcvtts[ds]2usi), SSE3 (fisttp),
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; SSE2 (cvtts[ds]2si) and vanilla X87 (fnstcw+fist, 32-bit only).
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;
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; RUN: llc < %s -mtriple=i386-pc-windows-msvc -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512_32
|
||||
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512_32
|
||||
; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512_64
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512_64
|
||||
; RUN: llc < %s -mtriple=i386-pc-windows-msvc -mattr=+sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE3_32
|
||||
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE3_32
|
||||
; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -mattr=+sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE3_64
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE3_64
|
||||
; RUN: llc < %s -mtriple=i386-pc-windows-msvc -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2_32
|
||||
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2_32
|
||||
; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2_64
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2_64
|
||||
; RUN: llc < %s -mtriple=i386-pc-windows-msvc -mattr=-sse | FileCheck %s --check-prefix=CHECK --check-prefix=X87
|
||||
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=-sse | FileCheck %s --check-prefix=CHECK --check-prefix=X87
|
||||
|
||||
; CHECK-LABEL: f_to_u64
|
||||
; X87-DAG: fsub
|
||||
; X87-DAG: fnstcw
|
||||
; X87: fist
|
||||
; SSE2_32-DAG: {{subss|fsub}}
|
||||
; SSE2_32-DAG: fnstcw
|
||||
; SSE2_32: fist
|
||||
; SSE2_64: subss
|
||||
; SSE2_64: cvttss2si
|
||||
; SSE3_32: {{subss|fsub}}
|
||||
; SSE3_32: fistt
|
||||
; SSE3_64: subss
|
||||
; SSE3_64: cvttss2si
|
||||
; AVX512_32: {{subss|fsub}}
|
||||
; AVX512_32: fistt
|
||||
; AVX512_64: vcvttss2usi
|
||||
; CHECK: ret
|
||||
define i64 @f_to_u64(float %a) nounwind {
|
||||
%r = fptoui float %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f_to_s64
|
||||
; X87: fnstcw
|
||||
; X87: fist
|
||||
; SSE2_32: fnstcw
|
||||
; SSE2_32: fist
|
||||
; SSE2_64: cvttss2si
|
||||
; SSE3_32: fistt
|
||||
; SSE3_64: cvttss2si
|
||||
; AVX512_32: fistt
|
||||
; AVX512_64: vcvttss2si
|
||||
; CHECK: ret
|
||||
define i64 @f_to_s64(float %a) nounwind {
|
||||
%r = fptosi float %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: d_to_u64
|
||||
; X87-DAG: fsub
|
||||
; X87-DAG: fnstcw
|
||||
; X87: fist
|
||||
; SSE2_32-DAG: {{subsd|fsub}}
|
||||
; SSE2_32-DAG: fnstcw
|
||||
; SSE2_32: fist
|
||||
; SSE2_64: subsd
|
||||
; SSE2_64: cvttsd2si
|
||||
; SSE3_32: {{subsd|fsub}}
|
||||
; SSE3_32: fistt
|
||||
; SSE3_64: subsd
|
||||
; SSE3_64: cvttsd2si
|
||||
; AVX512_32: {{subsd|fsub}}
|
||||
; AVX512_32: fistt
|
||||
; AVX512_64: vcvttsd2usi
|
||||
; CHECK: ret
|
||||
define i64 @d_to_u64(double %a) nounwind {
|
||||
%r = fptoui double %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: d_to_s64
|
||||
; X87: fnstcw
|
||||
; X87: fist
|
||||
; SSE2_32: fnstcw
|
||||
; SSE2_32: fist
|
||||
; SSE2_64: cvttsd2si
|
||||
; SSE3_32: fistt
|
||||
; SSE3_64: cvttsd2si
|
||||
; AVX512_32: fistt
|
||||
; AVX512_64: vcvttsd2si
|
||||
; CHECK: ret
|
||||
define i64 @d_to_s64(double %a) nounwind {
|
||||
%r = fptosi double %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: x_to_u64
|
||||
; CHECK-DAG: fsub
|
||||
; X87-DAG: fnstcw
|
||||
; SSE2_32-DAG: fnstcw
|
||||
; SSE2_64-DAG: fnstcw
|
||||
; CHECK: fist
|
||||
; CHECK: ret
|
||||
define i64 @x_to_u64(x86_fp80 %a) nounwind {
|
||||
%r = fptoui x86_fp80 %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: x_to_s64
|
||||
; X87: fnstcw
|
||||
; X87: fist
|
||||
; SSE2_32: fnstcw
|
||||
; SSE2_32: fist
|
||||
; SSE2_64: fnstcw
|
||||
; SSE2_64: fist
|
||||
; SSE3_32: fistt
|
||||
; SSE3_64: fistt
|
||||
; AVX512_32: fistt
|
||||
; AVX512_64: fistt
|
||||
; CHECK: ret
|
||||
define i64 @x_to_s64(x86_fp80 %a) nounwind {
|
||||
%r = fptosi x86_fp80 %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
|
@ -1,15 +1,17 @@
|
|||
; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=generic | FileCheck %s -check-prefix=FTOL
|
||||
; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=generic | FileCheck %s -check-prefix=COMPILERRT
|
||||
; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=COMPILERRT
|
||||
; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s -check-prefix=COMPILERRT
|
||||
; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=COMPILERRT
|
||||
; RUN: llc < %s -mtriple=x86_64-pc-mingw32 | FileCheck %s -check-prefix=COMPILERRT
|
||||
; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s -check-prefix=COMPILERRT
|
||||
; RUN: llc < %s -mattr=-sse -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=FTOL_2
|
||||
; RUN: llc < %s -mattr=-sse -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=COMPILERRT
|
||||
|
||||
; Win32 targets use the MSVCRT _ftol2 runtime function for fptoui to i64. This
|
||||
; function has a nonstandard calling convention: the input value is expected on
|
||||
; the x87 stack instead of the callstack. The input value is popped by the
|
||||
; callee. Mingw32 uses normal cdecl compiler-rt functions.
|
||||
; This test originally used the FTOL and FTOL_2 checks for the i686-pc-win32
|
||||
; triples, under the assumption that Win32 targets should use the MSVCRT
|
||||
; _ftol2 runtime function for fptoui to i64. That usage was incorrect,
|
||||
; as _ftol2 performs conversion to signed i64. As of the compiler fix,
|
||||
; the FTOL/FTOL_2 checks are no longer used, which basically renders
|
||||
; this test meaningless.
|
||||
|
||||
define i64 @double_ui64(double %x) nounwind {
|
||||
entry:
|
||||
|
|
|
|||
Loading…
Reference in New Issue