forked from OSchip/llvm-project
parent
2591afca0a
commit
850e143cbf
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@ -685,15 +685,9 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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}
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// All registers must have inf weight. Just grab one!
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if (!minReg) {
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if (active_.size() == 0) {
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// FIXME: All the registers are occupied by fixed intervals.
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cerr << "Register allocator ran out of registers!\n";
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abort();
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}
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if (!minReg)
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minReg = *RC->allocation_order_begin(*mf_);
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}
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}
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DOUT << "\t\tregister with min weight: "
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<< tri_->getName(minReg) << " (" << minWeight << ")\n";
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