forked from OSchip/llvm-project
function names should start with a lower case letter; NFC
llvm-svn: 250174
This commit is contained in:
Sanjay Patel
parent
722bcb08f1
commit
85030aa1bd
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@ -193,39 +193,39 @@ namespace {
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private:
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SDNode *Select(SDNode *N) override;
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SDNode *SelectGather(SDNode *N, unsigned Opc);
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SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
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SDNode *selectGather(SDNode *N, unsigned Opc);
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SDNode *selectAtomicLoadArith(SDNode *Node, MVT NVT);
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bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
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bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
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bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
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bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
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bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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bool foldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
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bool matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
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bool matchWrapper(SDValue N, X86ISelAddressMode &AM);
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bool matchAddress(SDValue N, X86ISelAddressMode &AM);
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bool matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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unsigned Depth);
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bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
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bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
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bool matchAddressBase(SDValue N, X86ISelAddressMode &AM);
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bool selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
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bool selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
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bool SelectLEAAddr(SDValue N, SDValue &Base,
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bool selectMOV64Imm32(SDValue N, SDValue &Imm);
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bool selectLEAAddr(SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
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bool selectLEA64_32Addr(SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
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bool selectTLSADDRAddr(SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectScalarSSELoad(SDNode *Root, SDValue N,
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bool selectScalarSSELoad(SDNode *Root, SDValue N,
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SDValue &Base, SDValue &Scale,
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SDValue &Index, SDValue &Disp,
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SDValue &Segment,
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SDValue &NodeWithChain);
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bool TryFoldLoad(SDNode *P, SDValue N,
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bool tryFoldLoad(SDNode *P, SDValue N,
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SDValue &Base, SDValue &Scale,
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SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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@ -235,7 +235,7 @@ namespace {
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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void EmitSpecialCodeForMain();
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void emitSpecialCodeForMain();
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inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,
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SDValue &Base, SDValue &Scale,
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@ -457,7 +457,7 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
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/// Replace the original chain operand of the call with
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/// load's chain operand and move load below the call's chain operand.
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static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
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static void moveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
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SDValue Call, SDValue OrigChain) {
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SmallVector<SDValue, 8> Ops;
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SDValue Chain = OrigChain.getOperand(0);
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@ -569,7 +569,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
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SDValue Load = N->getOperand(1);
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if (!isCalleeLoad(Load, Chain, HasCallSeq))
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continue;
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MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
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moveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
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++NumLoadMoved;
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continue;
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}
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@ -647,7 +647,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
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/// Emit any code that needs to be executed only in the main function.
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void X86DAGToDAGISel::EmitSpecialCodeForMain() {
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void X86DAGToDAGISel::emitSpecialCodeForMain() {
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if (Subtarget->isTargetCygMing()) {
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TargetLowering::ArgListTy Args;
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auto &DL = CurDAG->getDataLayout();
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@ -667,7 +667,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode() {
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// If this is main, emit special code for main.
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if (const Function *Fn = MF->getFunction())
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if (Fn->hasExternalLinkage() && Fn->getName() == "main")
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EmitSpecialCodeForMain();
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emitSpecialCodeForMain();
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}
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static bool isDispSafeForFrameIndex(int64_t Val) {
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@ -680,7 +680,7 @@ static bool isDispSafeForFrameIndex(int64_t Val) {
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return isInt<31>(Val);
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}
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bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
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bool X86DAGToDAGISel::foldOffsetIntoAddress(uint64_t Offset,
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X86ISelAddressMode &AM) {
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// Cannot combine ExternalSymbol displacements with integer offsets.
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if (Offset != 0 && (AM.ES || AM.MCSym))
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@ -702,7 +702,7 @@ bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
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}
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bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
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bool X86DAGToDAGISel::matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
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SDValue Address = N->getOperand(1);
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// load gs:0 -> GS segment register.
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@ -729,7 +729,7 @@ bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
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/// Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes into an addressing
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/// mode. These wrap things that will resolve down into a symbol reference.
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/// If no match is possible, this returns true, otherwise it returns false.
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bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
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// If the addressing mode already has a symbol as the displacement, we can
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// never match another symbol.
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if (AM.hasSymbolicDisplacement())
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@ -752,7 +752,7 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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X86ISelAddressMode Backup = AM;
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AM.GV = G->getGlobal();
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AM.SymbolFlags = G->getTargetFlags();
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if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
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if (foldOffsetIntoAddress(G->getOffset(), AM)) {
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AM = Backup;
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return true;
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}
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@ -761,7 +761,7 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.SymbolFlags = CP->getTargetFlags();
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if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
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if (foldOffsetIntoAddress(CP->getOffset(), AM)) {
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AM = Backup;
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return true;
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}
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@ -777,7 +777,7 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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X86ISelAddressMode Backup = AM;
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AM.BlockAddr = BA->getBlockAddress();
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AM.SymbolFlags = BA->getTargetFlags();
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if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
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if (foldOffsetIntoAddress(BA->getOffset(), AM)) {
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AM = Backup;
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return true;
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}
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@ -827,8 +827,8 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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/// Add the specified node to the specified addressing mode, returning true if
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/// it cannot be done. This just pattern matches for the addressing mode.
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bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
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if (MatchAddressRecursively(N, AM, 0))
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bool X86DAGToDAGISel::matchAddress(SDValue N, X86ISelAddressMode &AM) {
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if (matchAddressRecursively(N, AM, 0))
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return true;
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// Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
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@ -861,7 +861,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
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// the Pos node's ID. Note that this does *not* preserve the uniqueness of node
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// IDs! The selection DAG must no longer depend on their uniqueness when this
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// is used.
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static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
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static void insertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
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if (N.getNode()->getNodeId() == -1 ||
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N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
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DAG.RepositionNode(Pos.getNode(), N.getNode());
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@ -873,7 +873,7 @@ static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
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// safe. This allows us to convert the shift and and into an h-register
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// extract and a scaled index. Returns false if the simplification is
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// performed.
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static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
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static bool foldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
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uint64_t Mask,
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SDValue Shift, SDValue X,
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X86ISelAddressMode &AM) {
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@ -901,12 +901,12 @@ static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
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// these nodes. We continually insert before 'N' in sequence as this is
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// essentially a pre-flattened and pre-sorted sequence of nodes. There is no
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// hierarchy left to express.
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InsertDAGNode(DAG, N, Eight);
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InsertDAGNode(DAG, N, Srl);
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InsertDAGNode(DAG, N, NewMask);
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InsertDAGNode(DAG, N, And);
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InsertDAGNode(DAG, N, ShlCount);
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InsertDAGNode(DAG, N, Shl);
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insertDAGNode(DAG, N, Eight);
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insertDAGNode(DAG, N, Srl);
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insertDAGNode(DAG, N, NewMask);
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insertDAGNode(DAG, N, And);
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insertDAGNode(DAG, N, ShlCount);
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insertDAGNode(DAG, N, Shl);
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DAG.ReplaceAllUsesWith(N, Shl);
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AM.IndexReg = And;
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AM.Scale = (1 << ScaleLog);
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@ -916,7 +916,7 @@ static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
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// Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
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// allows us to fold the shift into this addressing mode. Returns false if the
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// transform succeeded.
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static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
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static bool foldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
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uint64_t Mask,
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SDValue Shift, SDValue X,
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X86ISelAddressMode &AM) {
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@ -946,9 +946,9 @@ static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
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// these nodes. We continually insert before 'N' in sequence as this is
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// essentially a pre-flattened and pre-sorted sequence of nodes. There is no
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// hierarchy left to express.
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InsertDAGNode(DAG, N, NewMask);
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InsertDAGNode(DAG, N, NewAnd);
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InsertDAGNode(DAG, N, NewShift);
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insertDAGNode(DAG, N, NewMask);
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insertDAGNode(DAG, N, NewAnd);
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insertDAGNode(DAG, N, NewShift);
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DAG.ReplaceAllUsesWith(N, NewShift);
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AM.Scale = 1 << ShiftAmt;
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@ -983,7 +983,7 @@ static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
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// Note that this function assumes the mask is provided as a mask *after* the
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// value is shifted. The input chain may or may not match that, but computing
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// such a mask is trivial.
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static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
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static bool foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
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uint64_t Mask,
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SDValue Shift, SDValue X,
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X86ISelAddressMode &AM) {
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@ -1039,7 +1039,7 @@ static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
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assert(X.getValueType() != VT);
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// We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
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SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
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InsertDAGNode(DAG, N, NewX);
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insertDAGNode(DAG, N, NewX);
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X = NewX;
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}
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SDLoc DL(N);
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@ -1053,10 +1053,10 @@ static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
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// these nodes. We continually insert before 'N' in sequence as this is
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// essentially a pre-flattened and pre-sorted sequence of nodes. There is no
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// hierarchy left to express.
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InsertDAGNode(DAG, N, NewSRLAmt);
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InsertDAGNode(DAG, N, NewSRL);
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InsertDAGNode(DAG, N, NewSHLAmt);
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InsertDAGNode(DAG, N, NewSHL);
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insertDAGNode(DAG, N, NewSRLAmt);
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insertDAGNode(DAG, N, NewSRL);
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insertDAGNode(DAG, N, NewSHLAmt);
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insertDAGNode(DAG, N, NewSHL);
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DAG.ReplaceAllUsesWith(N, NewSHL);
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AM.Scale = 1 << AMShiftAmt;
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@ -1064,7 +1064,7 @@ static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
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return false;
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}
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bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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unsigned Depth) {
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SDLoc dl(N);
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DEBUG({
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@ -1073,7 +1073,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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});
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// Limit recursion.
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if (Depth > 5)
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return MatchAddressBase(N, AM);
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return matchAddressBase(N, AM);
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// If this is already a %rip relative address, we can only merge immediates
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// into it. Instead of handling this in every case, we handle it here.
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@ -1086,7 +1086,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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return true;
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if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
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if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
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if (!foldOffsetIntoAddress(Cst->getSExtValue(), AM))
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return false;
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return true;
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}
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@ -1104,19 +1104,19 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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}
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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if (!FoldOffsetIntoAddress(Val, AM))
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if (!foldOffsetIntoAddress(Val, AM))
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return false;
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break;
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}
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case X86ISD::Wrapper:
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case X86ISD::WrapperRIP:
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if (!MatchWrapper(N, AM))
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if (!matchWrapper(N, AM))
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return false;
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break;
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case ISD::LOAD:
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if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
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if (!matchLoadInAddress(cast<LoadSDNode>(N), AM))
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return false;
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break;
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@ -1153,7 +1153,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
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uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
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if (!FoldOffsetIntoAddress(Disp, AM))
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if (!foldOffsetIntoAddress(Disp, AM))
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return false;
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}
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@ -1185,7 +1185,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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// Try to fold the mask and shift into the scale, and return false if we
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// succeed.
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if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
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if (!foldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
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return false;
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break;
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}
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@ -1219,7 +1219,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
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uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
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if (FoldOffsetIntoAddress(Disp, AM))
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if (foldOffsetIntoAddress(Disp, AM))
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Reg = N.getNode()->getOperand(0);
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} else {
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Reg = N.getNode()->getOperand(0);
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@ -1245,7 +1245,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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// Test if the LHS of the sub can be folded.
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X86ISelAddressMode Backup = AM;
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if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
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if (matchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
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AM = Backup;
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break;
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}
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@ -1293,8 +1293,8 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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AM.Scale = 1;
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// Insert the new nodes into the topological ordering.
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InsertDAGNode(*CurDAG, N, Zero);
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InsertDAGNode(*CurDAG, N, Neg);
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insertDAGNode(*CurDAG, N, Zero);
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insertDAGNode(*CurDAG, N, Neg);
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return false;
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}
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@ -1304,14 +1304,14 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
|
|||
HandleSDNode Handle(N);
|
||||
|
||||
X86ISelAddressMode Backup = AM;
|
||||
if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
|
||||
!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
|
||||
if (!matchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
|
||||
!matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
|
||||
return false;
|
||||
AM = Backup;
|
||||
|
||||
// Try again after commuting the operands.
|
||||
if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
|
||||
!MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
|
||||
if (!matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
|
||||
!matchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
|
||||
return false;
|
||||
AM = Backup;
|
||||
|
||||
|
|
@ -1338,8 +1338,8 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
|
|||
ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
|
||||
|
||||
// Start with the LHS as an addr mode.
|
||||
if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
|
||||
!FoldOffsetIntoAddress(CN->getSExtValue(), AM))
|
||||
if (!matchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
|
||||
!foldOffsetIntoAddress(CN->getSExtValue(), AM))
|
||||
return false;
|
||||
AM = Backup;
|
||||
}
|
||||
|
|
@ -1365,27 +1365,27 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
|
|||
uint64_t Mask = N.getConstantOperandVal(1);
|
||||
|
||||
// Try to fold the mask and shift into an extract and scale.
|
||||
if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
|
||||
if (!foldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
|
||||
return false;
|
||||
|
||||
// Try to fold the mask and shift directly into the scale.
|
||||
if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
|
||||
if (!foldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
|
||||
return false;
|
||||
|
||||
// Try to swap the mask and shift to place shifts which can be done as
|
||||
// a scale on the outside of the mask.
|
||||
if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
|
||||
if (!foldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
|
||||
return false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return MatchAddressBase(N, AM);
|
||||
return matchAddressBase(N, AM);
|
||||
}
|
||||
|
||||
/// Helper for MatchAddress. Add the specified node to the
|
||||
/// specified addressing mode without any further recursion.
|
||||
bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
|
||||
bool X86DAGToDAGISel::matchAddressBase(SDValue N, X86ISelAddressMode &AM) {
|
||||
// Is the base register already occupied?
|
||||
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
|
||||
// If so, check to see if the scale index register is set.
|
||||
|
|
@ -1405,7 +1405,7 @@ bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
|
|||
return false;
|
||||
}
|
||||
|
||||
bool X86DAGToDAGISel::SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
||||
bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
||||
SDValue &Scale, SDValue &Index,
|
||||
SDValue &Disp, SDValue &Segment) {
|
||||
|
||||
|
|
@ -1448,7 +1448,7 @@ bool X86DAGToDAGISel::SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
|||
/// Parent is the parent node of the addr operand that is being matched. It
|
||||
/// is always a load, store, atomic node, or null. It is only null when
|
||||
/// checking memory operands for inline asm nodes.
|
||||
bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
||||
bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
||||
SDValue &Scale, SDValue &Index,
|
||||
SDValue &Disp, SDValue &Segment) {
|
||||
X86ISelAddressMode AM;
|
||||
|
|
@ -1470,7 +1470,7 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
|||
AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
|
||||
}
|
||||
|
||||
if (MatchAddress(N, AM))
|
||||
if (matchAddress(N, AM))
|
||||
return false;
|
||||
|
||||
MVT VT = N.getSimpleValueType();
|
||||
|
|
@ -1493,7 +1493,7 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
|||
/// We also return:
|
||||
/// PatternChainNode: this is the matched node that has a chain input and
|
||||
/// output.
|
||||
bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
|
||||
bool X86DAGToDAGISel::selectScalarSSELoad(SDNode *Root,
|
||||
SDValue N, SDValue &Base,
|
||||
SDValue &Scale, SDValue &Index,
|
||||
SDValue &Disp, SDValue &Segment,
|
||||
|
|
@ -1505,7 +1505,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
|
|||
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
|
||||
IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
|
||||
LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
|
||||
if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
||||
if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
|
@ -1523,7 +1523,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
|
|||
IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
|
||||
// Okay, this is a zero extending load. Fold it.
|
||||
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
|
||||
if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
||||
if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
||||
return false;
|
||||
PatternNodeWithChain = SDValue(LD, 0);
|
||||
return true;
|
||||
|
|
@ -1532,7 +1532,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
|
|||
}
|
||||
|
||||
|
||||
bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
|
||||
bool X86DAGToDAGISel::selectMOV64Imm32(SDValue N, SDValue &Imm) {
|
||||
if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
|
||||
uint64_t ImmVal = CN->getZExtValue();
|
||||
if ((uint32_t)ImmVal != (uint64_t)ImmVal)
|
||||
|
|
@ -1561,10 +1561,10 @@ bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
|
|||
return TM.getCodeModel() == CodeModel::Small;
|
||||
}
|
||||
|
||||
bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
|
||||
bool X86DAGToDAGISel::selectLEA64_32Addr(SDValue N, SDValue &Base,
|
||||
SDValue &Scale, SDValue &Index,
|
||||
SDValue &Disp, SDValue &Segment) {
|
||||
if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
|
||||
if (!selectLEAAddr(N, Base, Scale, Index, Disp, Segment))
|
||||
return false;
|
||||
|
||||
SDLoc DL(N);
|
||||
|
|
@ -1601,7 +1601,7 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
|
|||
|
||||
/// Calls SelectAddr and determines if the maximal addressing
|
||||
/// mode it matches can be cost effectively emitted as an LEA instruction.
|
||||
bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
|
||||
bool X86DAGToDAGISel::selectLEAAddr(SDValue N,
|
||||
SDValue &Base, SDValue &Scale,
|
||||
SDValue &Index, SDValue &Disp,
|
||||
SDValue &Segment) {
|
||||
|
|
@ -1612,7 +1612,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
|
|||
SDValue Copy = AM.Segment;
|
||||
SDValue T = CurDAG->getRegister(0, MVT::i32);
|
||||
AM.Segment = T;
|
||||
if (MatchAddress(N, AM))
|
||||
if (matchAddress(N, AM))
|
||||
return false;
|
||||
assert (T == AM.Segment);
|
||||
AM.Segment = Copy;
|
||||
|
|
@ -1662,7 +1662,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
|
|||
}
|
||||
|
||||
/// This is only run on TargetGlobalTLSAddress nodes.
|
||||
bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
|
||||
bool X86DAGToDAGISel::selectTLSADDRAddr(SDValue N, SDValue &Base,
|
||||
SDValue &Scale, SDValue &Index,
|
||||
SDValue &Disp, SDValue &Segment) {
|
||||
assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
|
||||
|
|
@ -1686,7 +1686,7 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
|
|||
}
|
||||
|
||||
|
||||
bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
|
||||
bool X86DAGToDAGISel::tryFoldLoad(SDNode *P, SDValue N,
|
||||
SDValue &Base, SDValue &Scale,
|
||||
SDValue &Index, SDValue &Disp,
|
||||
SDValue &Segment) {
|
||||
|
|
@ -1695,7 +1695,7 @@ bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
|
|||
!IsLegalToFold(N, P, P, OptLevel))
|
||||
return false;
|
||||
|
||||
return SelectAddr(N.getNode(),
|
||||
return selectAddr(N.getNode(),
|
||||
N.getOperand(1), Base, Scale, Index, Disp, Segment);
|
||||
}
|
||||
|
||||
|
|
@ -1892,7 +1892,7 @@ static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
|
|||
return Val;
|
||||
}
|
||||
|
||||
SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
|
||||
SDNode *X86DAGToDAGISel::selectAtomicLoadArith(SDNode *Node, MVT NVT) {
|
||||
if (Node->hasAnyUseOfValue(0))
|
||||
return nullptr;
|
||||
|
||||
|
|
@ -1905,7 +1905,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
|
|||
SDValue Ptr = Node->getOperand(1);
|
||||
SDValue Val = Node->getOperand(2);
|
||||
SDValue Base, Scale, Index, Disp, Segment;
|
||||
if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
|
||||
if (!selectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
|
||||
return nullptr;
|
||||
|
||||
// Which index into the table.
|
||||
|
|
@ -1999,7 +1999,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
|
|||
|
||||
/// Test whether the given X86ISD::CMP node has any uses which require the SF
|
||||
/// or OF bits to be accurate.
|
||||
static bool HasNoSignedComparisonUses(SDNode *N) {
|
||||
static bool hasNoSignedComparisonUses(SDNode *N) {
|
||||
// Examine each user of the node.
|
||||
for (SDNode::use_iterator UI = N->use_begin(),
|
||||
UE = N->use_end(); UI != UE; ++UI) {
|
||||
|
|
@ -2163,7 +2163,7 @@ static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
|
|||
}
|
||||
|
||||
/// Customized ISel for GATHER operations.
|
||||
SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
|
||||
SDNode *X86DAGToDAGISel::selectGather(SDNode *Node, unsigned Opc) {
|
||||
// Operands of Gather: VSrc, Base, VIdx, VMask, Scale
|
||||
SDValue Chain = Node->getOperand(0);
|
||||
SDValue VSrc = Node->getOperand(2);
|
||||
|
|
@ -2273,7 +2273,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
|
||||
case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
|
||||
}
|
||||
SDNode *RetVal = SelectGather(Node, Opc);
|
||||
SDNode *RetVal = selectGather(Node, Opc);
|
||||
if (RetVal)
|
||||
// We already called ReplaceUses inside SelectGather.
|
||||
return nullptr;
|
||||
|
|
@ -2300,7 +2300,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
case ISD::ATOMIC_LOAD_AND:
|
||||
case ISD::ATOMIC_LOAD_OR:
|
||||
case ISD::ATOMIC_LOAD_ADD: {
|
||||
SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
|
||||
SDNode *RetVal = selectAtomicLoadArith(Node, NVT);
|
||||
if (RetVal)
|
||||
return RetVal;
|
||||
break;
|
||||
|
|
@ -2487,10 +2487,10 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
}
|
||||
|
||||
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
||||
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
||||
bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
||||
// Multiply is commmutative.
|
||||
if (!foldedLoad) {
|
||||
foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
||||
foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
||||
if (foldedLoad)
|
||||
std::swap(N0, N1);
|
||||
}
|
||||
|
|
@ -2632,7 +2632,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
}
|
||||
|
||||
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
||||
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
||||
bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
||||
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
|
||||
|
||||
SDValue InFlag;
|
||||
|
|
@ -2640,7 +2640,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
// Special case for div8, just use a move with zero extension to AX to
|
||||
// clear the upper 8 bits (AH).
|
||||
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
|
||||
if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
|
||||
if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
|
||||
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
|
||||
Move =
|
||||
SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
|
||||
|
|
@ -2775,7 +2775,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
SDValue N1 = Node->getOperand(1);
|
||||
|
||||
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
|
||||
HasNoSignedComparisonUses(Node))
|
||||
hasNoSignedComparisonUses(Node))
|
||||
N0 = N0.getOperand(0);
|
||||
|
||||
// Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
|
||||
|
|
@ -2792,7 +2792,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
// For example, convert "testl %eax, $8" to "testb %al, $8"
|
||||
if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
|
||||
(!(C->getZExtValue() & 0x80) ||
|
||||
HasNoSignedComparisonUses(Node))) {
|
||||
hasNoSignedComparisonUses(Node))) {
|
||||
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);
|
||||
SDValue Reg = N0.getNode()->getOperand(0);
|
||||
|
||||
|
|
@ -2826,7 +2826,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
// For example, "testl %eax, $2048" to "testb %ah, $8".
|
||||
if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
|
||||
(!(C->getZExtValue() & 0x8000) ||
|
||||
HasNoSignedComparisonUses(Node))) {
|
||||
hasNoSignedComparisonUses(Node))) {
|
||||
// Shift the immediate right by 8 bits.
|
||||
SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
|
||||
dl, MVT::i8);
|
||||
|
|
@ -2864,7 +2864,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
|
||||
N0.getValueType() != MVT::i16 &&
|
||||
(!(C->getZExtValue() & 0x8000) ||
|
||||
HasNoSignedComparisonUses(Node))) {
|
||||
hasNoSignedComparisonUses(Node))) {
|
||||
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
|
||||
MVT::i16);
|
||||
SDValue Reg = N0.getNode()->getOperand(0);
|
||||
|
|
@ -2887,7 +2887,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
|
||||
N0.getValueType() == MVT::i64 &&
|
||||
(!(C->getZExtValue() & 0x80000000) ||
|
||||
HasNoSignedComparisonUses(Node))) {
|
||||
hasNoSignedComparisonUses(Node))) {
|
||||
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
|
||||
MVT::i32);
|
||||
SDValue Reg = N0.getNode()->getOperand(0);
|
||||
|
|
@ -2937,7 +2937,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
|||
break;
|
||||
|
||||
SDValue Base, Scale, Index, Disp, Segment;
|
||||
if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
|
||||
if (!selectAddr(LoadNode, LoadNode->getBasePtr(),
|
||||
Base, Scale, Index, Disp, Segment))
|
||||
break;
|
||||
|
||||
|
|
@ -2986,7 +2986,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
|
|||
case InlineAsm::Constraint_v: // not offsetable ??
|
||||
case InlineAsm::Constraint_m: // memory
|
||||
case InlineAsm::Constraint_X:
|
||||
if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
|
||||
if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
|
||||
return true;
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -255,9 +255,9 @@ def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
|
|||
"", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
|
||||
|
||||
// This 64-bit pseudo-move can be used for both a 64-bit constant that is
|
||||
// actually the zero-extension of a 32-bit constant, and for labels in the
|
||||
// actually the zero-extension of a 32-bit constant and for labels in the
|
||||
// x86-64 small code model.
|
||||
def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
|
||||
def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
|
||||
|
||||
let AddedComplexity = 1 in
|
||||
def : Pat<(i64 mov64imm32:$src),
|
||||
|
|
|
|||
|
|
@ -512,10 +512,10 @@ def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
|
|||
// These are 'extloads' from a scalar to the low element of a vector, zeroing
|
||||
// the top elements. These are used for the SSE 'ss' and 'sd' instruction
|
||||
// forms.
|
||||
def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
|
||||
def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
|
||||
SDNPWantRoot]>;
|
||||
def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
|
||||
def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
|
||||
SDNPWantRoot]>;
|
||||
|
||||
|
|
|
|||
|
|
@ -695,34 +695,34 @@ def lea64mem : Operand<i64> {
|
|||
// X86 Complex Pattern Definitions.
|
||||
//
|
||||
|
||||
// Define X86 specific addressing mode.
|
||||
def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
|
||||
def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
|
||||
// Define X86-specific addressing mode.
|
||||
def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
|
||||
def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
|
||||
[add, sub, mul, X86mul_imm, shl, or, frameindex],
|
||||
[]>;
|
||||
// In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
|
||||
def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
|
||||
def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr",
|
||||
[add, sub, mul, X86mul_imm, shl, or,
|
||||
frameindex, X86WrapperRIP],
|
||||
[]>;
|
||||
|
||||
def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
|
||||
def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
|
||||
[tglobaltlsaddr], []>;
|
||||
|
||||
def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
|
||||
def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
|
||||
[tglobaltlsaddr], []>;
|
||||
|
||||
def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
|
||||
def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr",
|
||||
[add, sub, mul, X86mul_imm, shl, or, frameindex,
|
||||
X86WrapperRIP], []>;
|
||||
|
||||
def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
|
||||
def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
|
||||
[tglobaltlsaddr], []>;
|
||||
|
||||
def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
|
||||
def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
|
||||
[tglobaltlsaddr], []>;
|
||||
|
||||
def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>;
|
||||
def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86 Instruction Predicate Definitions.
|
||||
|
|
|
|||
Loading…
Reference in New Issue