maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 

(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

llvm-svn: 114679
This commit is contained in:
Jim Grosbach 2010-09-23 18:05:37 +00:00
parent 6366d1b858
commit 8503054410
3 changed files with 36 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -1209,6 +1209,16 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
} else
// TRAP and tTRAP need special handling for non-Darwin. The GNU binutils
// don't (yet) support the 'trap' mnemonic. (Use decimal, not hex, to
// be consistent with the MC instruction printer.)
// FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
// Need a way to ask "isTargetDarwin()" there, first, though.
if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
} else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
} else
printInstruction(MI, OS);
@ -1714,6 +1724,30 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
EmitJumpTable(MI);
return;
}
case ARM::TRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.
if (!Subtarget->isTargetDarwin()) {
//.long 0xe7ffdefe ${:comment} trap
uint32_t Val = 0xe7ffdefee;
OutStreamer.AddComment("trap");
OutStreamer.EmitIntValue(Val, 4);
return;
}
break;
}
case ARM::tTRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.
if (!Subtarget->isTargetDarwin()) {
//.long 0xe7ffdefe ${:comment} trap
uint32_t Val = 0xdefe;
OutStreamer.AddComment("trap");
OutStreamer.EmitIntValue(Val, 2);
return;
}
break;
}
}
MCInst TmpInst;

4
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -815,11 +815,9 @@ def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
}
// A5.4 Permanently UNDEFINED instructions.
// FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
// binutils
let isBarrier = 1, isTerminator = 1 in
def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
".long 0xe7ffdefe ${:comment} trap", [(trap)]>,
"trap", [(trap)]>,
Requires<[IsARM]> {
let Inst{27-25} = 0b011;
let Inst{24-20} = 0b11111;

4
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -411,11 +411,9 @@ def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
// A8.6.16 B: Encoding T1
// If Inst{11-8} == 0b1110 then UNDEFINED
// FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
// binutils
let isBarrier = 1, isTerminator = 1 in
def tTRAP : TI<(outs), (ins), IIC_Br,
".short 0xdefe ${:comment} trap", [(trap)]>, Encoding16 {
"trap", [(trap)]>, Encoding16 {
let Inst{15-12} = 0b1101;
let Inst{11-8} = 0b1110;
}