forked from OSchip/llvm-project
[AArch64] regenerate complete test checks; NFC
This commit is contained in:
Sanjay Patel
parent
256e61699b
commit
84e6fd815a
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@ -1,8 +1,11 @@
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @v_dup8(i8 %A) nounwind {
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;CHECK-LABEL: v_dup8:
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;CHECK: dup.8b
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; CHECK-LABEL: v_dup8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.8b v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
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%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
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%tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
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@ -15,8 +18,10 @@ define <8 x i8> @v_dup8(i8 %A) nounwind {
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}
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define <4 x i16> @v_dup16(i16 %A) nounwind {
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;CHECK-LABEL: v_dup16:
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;CHECK: dup.4h
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; CHECK-LABEL: v_dup16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.4h v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
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%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
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%tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
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@ -25,24 +30,31 @@ define <4 x i16> @v_dup16(i16 %A) nounwind {
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}
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define <2 x i32> @v_dup32(i32 %A) nounwind {
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;CHECK-LABEL: v_dup32:
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;CHECK: dup.2s
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; CHECK-LABEL: v_dup32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.2s v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
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%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
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ret <2 x i32> %tmp2
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}
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define <2 x float> @v_dupfloat(float %A) nounwind {
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;CHECK-LABEL: v_dupfloat:
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;CHECK: dup.2s
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; CHECK-LABEL: v_dupfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: dup.2s v0, v0[0]
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; CHECK-NEXT: ret
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%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
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%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
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ret <2 x float> %tmp2
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}
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define <16 x i8> @v_dupQ8(i8 %A) nounwind {
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;CHECK-LABEL: v_dupQ8:
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;CHECK: dup.16b
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; CHECK-LABEL: v_dupQ8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.16b v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
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%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
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%tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
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@ -63,8 +75,10 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwind {
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}
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define <8 x i16> @v_dupQ16(i16 %A) nounwind {
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;CHECK-LABEL: v_dupQ16:
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;CHECK: dup.8h
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; CHECK-LABEL: v_dupQ16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.8h v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
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%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
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%tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
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@ -77,8 +91,10 @@ define <8 x i16> @v_dupQ16(i16 %A) nounwind {
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}
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define <4 x i32> @v_dupQ32(i32 %A) nounwind {
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;CHECK-LABEL: v_dupQ32:
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;CHECK: dup.4s
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; CHECK-LABEL: v_dupQ32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.4s v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
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%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
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%tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
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@ -87,8 +103,11 @@ define <4 x i32> @v_dupQ32(i32 %A) nounwind {
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}
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define <4 x float> @v_dupQfloat(float %A) nounwind {
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;CHECK-LABEL: v_dupQfloat:
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;CHECK: dup.4s
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; CHECK-LABEL: v_dupQfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: dup.4s v0, v0[0]
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
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%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
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%tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2
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@ -99,160 +118,210 @@ define <4 x float> @v_dupQfloat(float %A) nounwind {
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; Check to make sure it works with shuffles, too.
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define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
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;CHECK-LABEL: v_shuffledup8:
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;CHECK: dup.8b
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; CHECK-LABEL: v_shuffledup8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.8b v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
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;CHECK-LABEL: v_shuffledup16:
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;CHECK: dup.4h
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; CHECK-LABEL: v_shuffledup16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.4h v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
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;CHECK-LABEL: v_shuffledup32:
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;CHECK: dup.2s
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; CHECK-LABEL: v_shuffledup32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.2s v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
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ret <2 x i32> %tmp2
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}
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define <2 x float> @v_shuffledupfloat(float %A) nounwind {
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;CHECK-LABEL: v_shuffledupfloat:
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;CHECK: dup.2s
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; CHECK-LABEL: v_shuffledupfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: dup.2s v0, v0[0]
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; CHECK-NEXT: ret
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%tmp1 = insertelement <2 x float> undef, float %A, i32 0
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
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ret <2 x float> %tmp2
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}
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define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ8:
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;CHECK: dup.16b
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; CHECK-LABEL: v_shuffledupQ8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.16b v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ16:
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;CHECK: dup.8h
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; CHECK-LABEL: v_shuffledupQ16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.8h v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ32:
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;CHECK: dup.4s
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; CHECK-LABEL: v_shuffledupQ32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup.4s v0, w0
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %tmp2
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}
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define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
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;CHECK-LABEL: v_shuffledupQfloat:
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;CHECK: dup.4s
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; CHECK-LABEL: v_shuffledupQfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: dup.4s v0, v0[0]
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x float> undef, float %A, i32 0
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %tmp2
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}
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define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vduplane8:
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;CHECK: dup.8b
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; CHECK-LABEL: vduplane8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.8b v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vduplane16:
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;CHECK: dup.4h
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; CHECK-LABEL: vduplane16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.4h v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vduplane32:
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;CHECK: dup.2s
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; CHECK-LABEL: vduplane32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.2s v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vduplanefloat:
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;CHECK: dup.2s
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; CHECK-LABEL: vduplanefloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.2s v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ8:
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;CHECK: dup.16b
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; CHECK-LABEL: vduplaneQ8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.16b v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ16:
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;CHECK: dup.8h
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; CHECK-LABEL: vduplaneQ16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.8h v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ32:
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;CHECK: dup.4s
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; CHECK-LABEL: vduplaneQ32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.4s v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vduplaneQfloat:
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;CHECK: dup.4s
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; CHECK-LABEL: vduplaneQfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: dup.4s v0, v0[1]
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; CHECK-NEXT: ret
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x float> %tmp2
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}
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define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: foo:
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;CHECK: dup.2d
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; CHECK-LABEL: foo:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup.2d v0, v0[1]
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; CHECK-NEXT: ret
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x i64> %0
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}
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define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: bar:
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;CHECK: dup.2d
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; CHECK-LABEL: bar:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup.2d v0, v0[0]
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; CHECK-NEXT: ret
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x i64> %0
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}
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define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: baz:
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;CHECK: dup.2d
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; CHECK-LABEL: baz:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup.2d v0, v0[1]
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; CHECK-NEXT: ret
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %0
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}
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define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: qux:
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;CHECK: dup.2d
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; CHECK-LABEL: qux:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup.2d v0, v0[0]
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; CHECK-NEXT: ret
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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@ -260,9 +329,11 @@ entry:
|
|||
|
||||
define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {
|
||||
; CHECK-LABEL: f:
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: mov.s v0[1], w1
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: mov.s v0[1], w1
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
|
||||
; CHECK-NEXT: ret
|
||||
%vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
|
||||
%vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
|
||||
ret <2 x i32> %vecinit1
|
||||
|
|
@ -270,11 +341,12 @@ define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {
|
|||
|
||||
define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
|
||||
; CHECK-LABEL: g:
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: mov.s v0[1], w1
|
||||
; CHECK-NEXT: mov.s v0[2], w1
|
||||
; CHECK-NEXT: mov.s v0[3], w0
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: mov.s v0[1], w1
|
||||
; CHECK-NEXT: mov.s v0[2], w1
|
||||
; CHECK-NEXT: mov.s v0[3], w0
|
||||
; CHECK-NEXT: ret
|
||||
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
|
||||
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
|
||||
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
|
||||
|
|
@ -284,9 +356,10 @@ define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
|
|||
|
||||
define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
|
||||
; CHECK-LABEL: h:
|
||||
; CHECK-NEXT: fmov d0, x0
|
||||
; CHECK-NEXT: mov.d v0[1], x1
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmov d0, x0
|
||||
; CHECK-NEXT: mov.d v0[1], x1
|
||||
; CHECK-NEXT: ret
|
||||
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
|
||||
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
|
||||
ret <2 x i64> %vecinit1
|
||||
|
|
@ -301,7 +374,9 @@ define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
|
|||
; *However*, it is a dup vD.4h, vN.h[2*idx].
|
||||
define <4 x i16> @test_build_illegal(<4 x i32> %in) {
|
||||
; CHECK-LABEL: test_build_illegal:
|
||||
; CHECK: dup.4h v0, v0[6]
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: dup.4h v0, v0[6]
|
||||
; CHECK-NEXT: ret
|
||||
%val = extractelement <4 x i32> %in, i32 3
|
||||
%smallval = trunc i32 %val to i16
|
||||
%vec = insertelement <4x i16> undef, i16 %smallval, i32 3
|
||||
|
|
@ -314,7 +389,9 @@ define <4 x i16> @test_build_illegal(<4 x i32> %in) {
|
|||
; the formation of an indexed-by-7 MLS.
|
||||
define <4 x i16> @test_high_splat(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 {
|
||||
; CHECK-LABEL: test_high_splat:
|
||||
; CHECK: mls.4h v0, v1, v2[7]
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mls.4h v0, v1, v2[7]
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
|
||||
%mul = mul <4 x i16> %shuffle, %b
|
||||
|
|
@ -324,37 +401,44 @@ entry:
|
|||
|
||||
; Also test the DUP path in the PerfectShuffle generator.
|
||||
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4i16:
|
||||
; CHECK-NEXT: dup.4h v0, v0[0]
|
||||
; CHECK-NEXT: ext.8b v0, v0, v1, #4
|
||||
define <4 x i16> @test_perfectshuffle_dupext_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: dup.4h v0, v0[0]
|
||||
; CHECK-NEXT: ext.8b v0, v0, v1, #4
|
||||
; CHECK-NEXT: ret
|
||||
%r = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4f16:
|
||||
; CHECK-NEXT: dup.4h v0, v0[0]
|
||||
; CHECK-NEXT: ext.8b v0, v0, v1, #4
|
||||
; CHECK-NEXT: ret
|
||||
define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b) nounwind {
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: dup.4h v0, v0[0]
|
||||
; CHECK-NEXT: ext.8b v0, v0, v1, #4
|
||||
; CHECK-NEXT: ret
|
||||
%r = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
|
||||
ret <4 x half> %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4i32:
|
||||
; CHECK-NEXT: dup.4s v0, v0[0]
|
||||
; CHECK-NEXT: ext.16b v0, v0, v1, #8
|
||||
; CHECK-NEXT: ret
|
||||
define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: dup.4s v0, v0[0]
|
||||
; CHECK-NEXT: ext.16b v0, v0, v1, #8
|
||||
; CHECK-NEXT: ret
|
||||
%r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4f32:
|
||||
; CHECK-NEXT: dup.4s v0, v0[0]
|
||||
; CHECK-NEXT: ext.16b v0, v0, v1, #8
|
||||
; CHECK-NEXT: ret
|
||||
define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind {
|
||||
; CHECK-LABEL: test_perfectshuffle_dupext_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: dup.4s v0, v0[0]
|
||||
; CHECK-NEXT: ext.16b v0, v0, v1, #8
|
||||
; CHECK-NEXT: ret
|
||||
%r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue