forked from OSchip/llvm-project
parent
724b81087d
commit
84e5bf0c95
llvm/lib/Target/X86
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@ -42985,6 +42985,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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// GCC Constraint Letters
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switch (Constraint[0]) {
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default: break;
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// 'A' means [ER]AX + [ER]DX.
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case 'A':
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if (Subtarget.is64Bit())
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return std::make_pair(X86::RAX, &X86::GR64_ADRegClass);
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assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
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"Expecting 64, 32 or 16 bit subtarget");
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return std::make_pair(X86::EAX, &X86::GR32_ADRegClass);
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// TODO: Slight differences here in allocation order and leaving
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// RIP in the class. Do they matter any more here than they do
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// in the normal allocation?
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@ -43184,14 +43192,6 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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if (StringRef("{fpsr}").equals_lower(Constraint))
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return std::make_pair(X86::FPSW, &X86::FPCCRRegClass);
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// 'A' means [ER]AX + [ER]DX.
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if (Constraint == "A") {
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if (Subtarget.is64Bit())
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return std::make_pair(X86::RAX, &X86::GR64_ADRegClass);
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assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
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"Expecting 64, 32 or 16 bit subtarget");
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return std::make_pair(X86::EAX, &X86::GR32_ADRegClass);
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}
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return Res;
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}
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