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[AVR] Rename 'ZREGS' to 'ZREG' 

It will only ever contain one register.

llvm-svn: 307620
This commit is contained in:
Dylan McKay 2017-07-11 04:53:43 +00:00
parent 96fdc65dc4
commit 84dd12d99e
3 changed files with 13 additions and 16 deletions
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22
llvm/lib/Target/AVR/AVRInstrInfo.td
View File

@ -1411,7 +1411,7 @@ hasSideEffects = 0 in
def LPMRdZ : FLPMX<0,
0,
(outs GPR8:$dst),
(ins ZREGS:$z),
(ins ZREG:$z),
"lpm\t$dst, $z",
[]>,
Requires<[HasLPMX]>;
@ -1423,19 +1423,19 @@ hasSideEffects = 0 in
def LPMRdZPi : FLPMX<0,
1,
(outs GPR8:$dst),
(ins ZREGS:$z),
(ins ZREG:$z),
"lpm\t$dst, $z+",
[]>,
Requires<[HasLPMX]>;
def LPMWRdZ : Pseudo<(outs DREGS:$dst),
(ins ZREGS:$z),
(ins ZREG:$z),
"lpmw\t$dst, $z",
[]>,
Requires<[HasLPMX]>;
def LPMWRdZPi : Pseudo<(outs DREGS:$dst),
(ins ZREGS:$z),
(ins ZREG:$z),
"lpmw\t$dst, $z+",
[]>,
Requires<[HasLPMX]>;
@ -1458,7 +1458,7 @@ hasSideEffects = 0 in
def ELPMRdZ : FLPMX<1,
0,
(outs GPR8:$dst),
(ins ZREGS:$z),
(ins ZREG:$z),
"elpm\t$dst, $z",
[]>,
Requires<[HasELPMX]>;
@ -1467,7 +1467,7 @@ hasSideEffects = 0 in
def ELPMRdZPi : FLPMX<1,
1,
(outs GPR8:$dst),
(ins ZREGS: $z),
(ins ZREG: $z),
"elpm\t$dst, $z+",
[]>,
Requires<[HasELPMX]>;
@ -1487,7 +1487,7 @@ let Uses = [R1, R0] in
let Defs = [R31R30] in
def SPMZPi : F16<0b1001010111111000,
(outs),
(ins ZREGS:$z),
(ins ZREG:$z),
"spm $z+",
[]>,
Requires<[HasSPMX]>;
@ -1564,28 +1564,28 @@ hasSideEffects = 0 in
// Read-Write-Modify (RMW) instructions.
def XCHZRd : FZRd<0b100,
(outs GPR8:$rd),
(ins ZREGS:$z),
(ins ZREG:$z),
"xch\t$z, $rd",
[]>,
Requires<[SupportsRMW]>;
def LASZRd : FZRd<0b101,
(outs GPR8:$rd),
(ins ZREGS:$z),
(ins ZREG:$z),
"las\t$z, $rd",
[]>,
Requires<[SupportsRMW]>;
def LACZRd : FZRd<0b110,
(outs GPR8:$rd),
(ins ZREGS:$z),
(ins ZREG:$z),
"lac\t$z, $rd",
[]>,
Requires<[SupportsRMW]>;
def LATZRd : FZRd<0b111,
(outs GPR8:$rd),
(ins ZREGS:$z),
(ins ZREG:$z),
"lat\t$z, $rd",
[]>,
Requires<[SupportsRMW]>;

5
llvm/lib/Target/AVR/AVRRegisterInfo.td
View File

@ -110,8 +110,6 @@ CoveredBySubRegs = 1 in
// Register Classes
//===----------------------------------------------------------------------===//
//:TODO: use proper set instructions instead of using always "add"
// Main 8-bit register class.
def GPR8 : RegisterClass<"AVR", [i8], 8,
(
@ -199,8 +197,7 @@ def PTRDISPREGS : RegisterClass<"AVR", [i16], 8,
// We have a bunch of instructions with an explicit Z register argument. We
// model this using a register class containing only the Z register.
// :TODO: Rename to 'ZREG'.
def ZREGS : RegisterClass<"AVR", [i16], 8, (add R31R30)>;
def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>;
// Register class used for the stack read pseudo instruction.
def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>;

2
llvm/lib/Target/AVR/InstPrinter/AVRInstPrinter.cpp
View File

@ -106,7 +106,7 @@ void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (Op.isReg()) {
bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
(MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
(MOI.RegClass == AVR::ZREGSRegClassID);
(MOI.RegClass == AVR::ZREGRegClassID);
if (isPtrReg) {
O << getRegisterName(Op.getReg(), AVR::ptr);