forked from OSchip/llvm-project
[GlobalISel][IRTranslator] When translating vector geps, splat the base pointer if required.
We can have geps that have a scalar base pointer, and a vector index value, which means that the base pointer must be splatted into a vector of pointers. This fixes crashes on arm64 GlobalISel with optimizations enabled.
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@ -1062,6 +1062,18 @@ bool IRTranslator::translateGetElementPtr(const User &U,
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if (auto *VT = dyn_cast<VectorType>(U.getType()))
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VectorWidth = VT->getNumElements();
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// We might need to splat the base pointer into a vector if the offsets
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// are vectors.
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if (VectorWidth && !PtrTy.isVector()) {
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BaseReg =
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MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg)
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.getReg(0);
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PtrIRTy = VectorType::get(PtrIRTy, VectorWidth);
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PtrTy = getLLTForType(*PtrIRTy, *DL);
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OffsetIRTy = DL->getIntPtrType(PtrIRTy);
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OffsetTy = getLLTForType(*OffsetIRTy, *DL);
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}
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int64_t Offset = 0;
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for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
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GTI != E; ++GTI) {
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@ -117,3 +117,24 @@ define i32* @var_then_const(%type1* %addr, i64 %idx) {
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%res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
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ret i32* %res
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}
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@arr = external global [8 x i32]
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define <2 x i32*> @vec_gep_scalar_base(<2 x i64> %offs) {
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; CHECK-LABEL: name: vec_gep_scalar_base
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; CHECK: bb.1.entry:
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @arr
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[GV]](p0), [[GV]](p0)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
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; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[COPY]], [[BUILD_VECTOR1]]
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY [[PTR_ADD]](<2 x p0>)
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; CHECK: $q0 = COPY [[COPY1]](<2 x p0>)
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; CHECK: RET_ReallyLR implicit $q0
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entry:
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%0 = getelementptr inbounds [8 x i32], [8 x i32]* @arr, i64 0, <2 x i64> %offs
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ret <2 x i32*> %0
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}
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