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Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" 

Add missing REQUIRES line to
prelegalizer-combiner-icmp-to-true-false-known-bits.
This commit is contained in:
Jessica Paquette 2021-05-19 09:18:52 -07:00
parent 4ca6e37b98
commit 84ae1cf8ed
15 changed files with 4812 additions and 6823 deletions
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4
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
View File

@ -513,6 +513,10 @@ public:
bool matchRotateOutOfRange(MachineInstr &MI);
void applyRotateOutOfRange(MachineInstr &MI);
/// \returns true if a G_ICMP instruction \p MI can be replaced with a true
/// or false constant based off of KnownBits information.
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
/// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI);

9
llvm/include/llvm/Target/GlobalISel/Combine.td
View File

@ -114,6 +114,7 @@ class GIApplyKind;
class GIApplyKindWithArgs;
def register_matchinfo: GIDefMatchData<"Register">;
def int64_matchinfo: GIDefMatchData<"int64_t">;
def build_fn_matchinfo :
GIDefMatchData<"std::function<void(MachineIRBuilder &)>">;
@ -613,6 +614,12 @@ def rotate_out_of_range : GICombineRule<
(apply [{ Helper.applyRotateOutOfRange(*${root}); }])
>;
def icmp_to_true_false_known_bits : GICombineRule<
(defs root:$d, int64_matchinfo:$matchinfo),
(match (wip_match_opcode G_ICMP):$d,
[{ return Helper.matchICmpToTrueFalseKnownBits(*${d}, ${matchinfo}); }]),
(apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>;
def funnel_shift_combines : GICombineGroup<[funnel_shift_to_rotate]>;
// FIXME: These should use the custom predicate feature once it lands.
@ -634,7 +641,7 @@ def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p]>;
def known_bits_simplifications : GICombineGroup<[
redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask,
zext_trunc_fold]>;
zext_trunc_fold, icmp_to_true_false_known_bits]>;
def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend]>;

53
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
View File

@ -3926,6 +3926,59 @@ void CombinerHelper::applyRotateOutOfRange(MachineInstr &MI) {
Observer.changedInstr(MI);
}
bool CombinerHelper::matchICmpToTrueFalseKnownBits(MachineInstr &MI,
int64_t &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_ICMP);
auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
auto KnownLHS = KB->getKnownBits(MI.getOperand(2).getReg());
auto KnownRHS = KB->getKnownBits(MI.getOperand(3).getReg());
Optional<bool> KnownVal;
switch (Pred) {
default:
llvm_unreachable("Unexpected G_ICMP predicate?");
case CmpInst::ICMP_EQ:
KnownVal = KnownBits::eq(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_NE:
KnownVal = KnownBits::ne(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_SGE:
KnownVal = KnownBits::sge(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_SGT:
KnownVal = KnownBits::sgt(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_SLE:
KnownVal = KnownBits::sle(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_SLT:
KnownVal = KnownBits::slt(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_UGE:
KnownVal = KnownBits::uge(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_UGT:
KnownVal = KnownBits::ugt(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_ULE:
KnownVal = KnownBits::ule(KnownLHS, KnownRHS);
break;
case CmpInst::ICMP_ULT:
KnownVal = KnownBits::ult(KnownLHS, KnownRHS);
break;
}
if (!KnownVal)
return false;
MatchInfo =
*KnownVal
? getICmpTrueVal(getTargetLowering(),
/*IsVector = */
MRI.getType(MI.getOperand(0).getReg()).isVector(),
/* IsFP = */ false)
: 0;
return true;
}
bool CombinerHelper::tryCombine(MachineInstr &MI) {
if (tryCombineCopy(MI))
return true;

3
llvm/lib/Target/AArch64/AArch64Combine.td
View File

@ -210,6 +210,7 @@ def AArch64PostLegalizerCombinerHelper
redundant_and, xor_of_and_with_same_reg,
extractvecelt_pairwise_add, redundant_or,
mul_const, redundant_sext_inreg,
form_bitfield_extract, rotate_out_of_range]> {
form_bitfield_extract, rotate_out_of_range,
icmp_to_true_false_known_bits]> {
let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
}

576
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir Normal file
View File

@ -0,0 +1,576 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombinerhelper-only-enable-rule="icmp_to_true_false_known_bits" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
# REQUIRES: asserts
--- |
define i1 @eq_true(i32* %ptr) { unreachable }
define i1 @ne_true(i32* %ptr) { unreachable }
define i1 @sge_true(i32* %ptr) { unreachable }
define i1 @sgt_true(i32* %ptr) { unreachable }
define i1 @sle_true(i32* %ptr) { unreachable }
define i1 @slt_true(i32* %ptr) { unreachable }
define i1 @uge_true(i32* %ptr) { unreachable }
define i1 @ugt_true(i32* %ptr) { unreachable }
define i1 @ule_true(i32* %ptr) { unreachable }
define i1 @ult_true(i32* %ptr) { unreachable }
define i1 @eq_false(i32* %ptr) { unreachable }
define i1 @ne_false(i32* %ptr) { unreachable }
define i1 @sge_false(i32* %ptr) { unreachable }
define i1 @sgt_false(i32* %ptr) { unreachable }
define i1 @sle_false(i32* %ptr) { unreachable }
define i1 @slt_false(i32* %ptr) { unreachable }
define i1 @uge_false(i32* %ptr) { unreachable }
define i1 @ugt_false(i32* %ptr) { unreachable }
define i1 @ule_false(i32* %ptr) { unreachable }
define i1 @ult_false(i32* %ptr) { unreachable }
define i1 @eq_unknown(i32* %ptr) { unreachable }
define i1 @ne_unknown(i32* %ptr) { unreachable }
define i1 @vector_true(i32* %ptr) { unreachable }
define i1 @vector_false(i32* %ptr) { unreachable }
!0 = !{i32 1, i32 2}
!1 = !{i32 1, i32 3}
...
---
name: eq_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: eq_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%cmp:_(s1) = G_ICMP intpred(eq), %cst(s32), %cst
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ne_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ne_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst_1:_(s32) = G_CONSTANT i32 1
%cst_2:_(s32) = G_CONSTANT i32 2
%cmp:_(s1) = G_ICMP intpred(ne), %cst_1(s32), %cst_2
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sge_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sge_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 2
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(sge), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sgt_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sgt_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 3
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(sgt), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sle_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sle_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(sle), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: slt_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: slt_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 -1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(slt), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: uge_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: uge_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 2
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(uge), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ugt_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ugt_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 -1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(ugt), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ule_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ule_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ult_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ult_true
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 0
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: eq_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: eq_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 0
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(eq), %load_eq_1(s32), %cst
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ne_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ne_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst_1:_(s32) = G_CONSTANT i32 1
%cst_2:_(s32) = G_CONSTANT i32 1
%cmp:_(s1) = G_ICMP intpred(ne), %cst_1(s32), %cst_2
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sge_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sge_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 -1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(sge), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sgt_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sgt_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(sgt), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sle_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sle_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 3
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(sle), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: slt_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: slt_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 2
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(slt), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: uge_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: uge_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 0
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(uge), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ugt_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ugt_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(ugt), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ule_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ule_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 -1
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ult_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ult_false
; CHECK: liveins: $x0
; CHECK: %cmp:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 2
%load_eq_1:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !0)
%cmp:_(s1) = G_ICMP intpred(ule), %cst, %load_eq_1(s32)
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: eq_unknown
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: eq_unknown
; CHECK: liveins: $x0
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: %cst:_(s32) = G_CONSTANT i32 1
; CHECK: %load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4,
; CHECK: %cmp:_(s1) = G_ICMP intpred(eq), %load_between_1_2(s32), %cst
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !1)
%cmp:_(s1) = G_ICMP intpred(eq), %load_between_1_2(s32), %cst
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: ne_unknown
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: ne_unknown
; CHECK: liveins: $x0
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: %cst:_(s32) = G_CONSTANT i32 1
; CHECK: %load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4,
; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %load_between_1_2(s32), %cst
; CHECK: %cmp_ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK: $w0 = COPY %cmp_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%load_between_1_2:_(s32) = G_LOAD %ptr(p0) :: (load 4, !range !1)
%cmp:_(s1) = G_ICMP intpred(ne), %load_between_1_2(s32), %cst
%cmp_ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %cmp_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: vector_true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: vector_true
; CHECK: liveins: $x0
; CHECK: %cst:_(s32) = G_CONSTANT i32 1
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32)
; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1)
; CHECK: $w0 = COPY %extract_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
%cmp:_(<2 x s1>) = G_ICMP intpred(eq), %bv(<2 x s32>), %bv
%extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32)
%extract_ext:_(s32) = G_ZEXT %extract(s1)
$w0 = COPY %extract_ext(s32)
RET_ReallyLR implicit $w0
...
---
name: vector_false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: vector_false
; CHECK: liveins: $x0
; CHECK: %cst:_(s32) = G_CONSTANT i32 1
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32)
; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1)
; CHECK: $w0 = COPY %extract_ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%ptr:_(p0) = COPY $x0
%cst:_(s32) = G_CONSTANT i32 1
%bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
%cmp:_(<2 x s1>) = G_ICMP intpred(ne), %bv(<2 x s32>), %bv
%extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32)
%extract_ext:_(s32) = G_ZEXT %extract(s1)
$w0 = COPY %extract_ext(s32)
RET_ReallyLR implicit $w0

17
llvm/test/CodeGen/AArch64/fold-global-offsets.ll
View File

@ -134,15 +134,14 @@ define i32 @f7() {
; GISEL-NEXT: mov w9, #64
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: sub x8, x9, #64 // =64
; GISEL-NEXT: fmov x11, d1
; GISEL-NEXT: fmov x10, d0
; GISEL-NEXT: lsl x12, x11, x8
; GISEL-NEXT: cmp x9, #64 // =64
; GISEL-NEXT: lsr x8, x11, x8
; GISEL-NEXT: orr x11, x12, x10, lsr #0
; GISEL-NEXT: csel x8, x11, x8, lo
; GISEL-NEXT: cmp x9, #0 // =0
; GISEL-NEXT: csel x8, x10, x8, eq
; GISEL-NEXT: fmov x10, d1
; GISEL-NEXT: fmov x9, d0
; GISEL-NEXT: lsl x11, x10, x8
; GISEL-NEXT: lsr x8, x10, x8
; GISEL-NEXT: orr x10, x11, x9, lsr #0
; GISEL-NEXT: tst wzr, #0x1
; GISEL-NEXT: csel x8, x10, x8, ne
; GISEL-NEXT: csel x8, x9, x8, ne
; GISEL-NEXT: ldr w0, [x8, #20]
; GISEL-NEXT: ret

104
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
View File

@ -1137,72 +1137,64 @@ define float @v_test_sitofp_i64_byte_to_f32(i64 %arg0) {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_movk_i32 s6, 0xff
; SI-NEXT: v_and_b32_e32 v2, s6, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 0, v2
; SI-NEXT: v_ffbh_u32_e32 v4, v2
; SI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v4
; SI-NEXT: v_ffbh_u32_e32 v5, v3
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; SI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; SI-NEXT: v_mov_b32_e32 v5, 0xbe
; SI-NEXT: v_sub_i32_e32 v6, vcc, v5, v4
; SI-NEXT: v_lshl_b64 v[4:5], v[2:3], v4
; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; SI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v5
; SI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
; SI-NEXT: v_and_b32_e32 v5, s6, v3
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 23, v2
; SI-NEXT: v_and_b32_e32 v0, s6, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 0, v0
; SI-NEXT: v_ffbh_u32_e32 v2, v0
; SI-NEXT: v_addc_u32_e64 v1, s[4:5], 0, 0, vcc
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; SI-NEXT: v_ffbh_u32_e32 v3, v1
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; SI-NEXT: v_mov_b32_e32 v3, 0xbe
; SI-NEXT: v_sub_i32_e32 v4, vcc, v3, v2
; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3
; SI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; SI-NEXT: v_and_b32_e32 v3, s6, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 23, v0
; SI-NEXT: s_mov_b32 s4, 0
; SI-NEXT: s_movk_i32 s5, 0x80
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[4:5]
; SI-NEXT: v_and_b32_e32 v3, 1, v2
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; SI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[4:5]
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: v_cndmask_b32_e64 v3, v3, 1, vcc
; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, v2, -v2, vcc
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[2:3]
; SI-NEXT: v_and_b32_e32 v1, 1, v0
; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3]
; SI-NEXT: v_cndmask_b32_e64 v1, v1, 1, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_test_sitofp_i64_byte_to_f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s6, 0xff
; VI-NEXT: v_and_b32_e32 v2, s6, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, 0, v2
; VI-NEXT: v_ffbh_u32_e32 v4, v2
; VI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v4
; VI-NEXT: v_ffbh_u32_e32 v5, v3
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; VI-NEXT: v_mov_b32_e32 v5, 0xbe
; VI-NEXT: v_sub_u32_e32 v6, vcc, v5, v4
; VI-NEXT: v_lshlrev_b64 v[4:5], v4, v[2:3]
; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v5
; VI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
; VI-NEXT: v_and_b32_e32 v5, s6, v3
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; VI-NEXT: v_lshlrev_b32_e32 v2, 23, v2
; VI-NEXT: v_and_b32_e32 v0, s6, v0
; VI-NEXT: v_add_u32_e32 v0, vcc, 0, v0
; VI-NEXT: v_ffbh_u32_e32 v2, v0
; VI-NEXT: v_addc_u32_e64 v1, s[4:5], 0, 0, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v2
; VI-NEXT: v_ffbh_u32_e32 v3, v1
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; VI-NEXT: v_mov_b32_e32 v3, 0xbe
; VI-NEXT: v_sub_u32_e32 v4, vcc, v3, v2
; VI-NEXT: v_lshlrev_b64 v[2:3], v2, v[0:1]
; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v3
; VI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; VI-NEXT: v_and_b32_e32 v3, s6, v1
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_lshlrev_b32_e32 v0, 23, v0
; VI-NEXT: s_mov_b32 s4, 0
; VI-NEXT: s_movk_i32 s5, 0x80
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[4:5]
; VI-NEXT: v_and_b32_e32 v3, 1, v2
; VI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[4:5]
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_cndmask_b32_e64 v3, v3, 1, vcc
; VI-NEXT: v_mov_b32_e32 v1, v0
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; VI-NEXT: v_cndmask_b32_e64 v0, v2, -v2, vcc
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[2:3]
; VI-NEXT: v_and_b32_e32 v1, 1, v0
; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3]
; VI-NEXT: v_cndmask_b32_e64 v1, v1, 1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
%masked = and i64 %arg0, 255
%itofp = sitofp i64 %masked to float

1918
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
View File

File diff suppressed because it is too large Load Diff

2185
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
View File

File diff suppressed because it is too large Load Diff

2172
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
View File

File diff suppressed because it is too large Load Diff

88
llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
View File

@ -1073,6 +1073,7 @@ define i64 @v_sdiv_i64_pow2k_denom(i64 %num) {
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
@ -1164,21 +1165,20 @@ define i64 @v_sdiv_i64_pow2k_denom(i64 %num) {
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v6
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
; CHECK-NEXT: v_mov_b32_e32 v7, s7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5]
; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v8, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6
@ -1524,14 +1524,14 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
@ -1562,7 +1562,7 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
@ -1587,7 +1587,7 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
@ -1609,26 +1609,26 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
; CGP-NEXT: v_mul_hi_u32 v12, s7, v7
; CGP-NEXT: v_mul_lo_u32 v11, s7, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11
; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_mov_b32_e32 v11, s8
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v12, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc
; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10
@ -1737,26 +1737,26 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v8, s7, v5
; CGP-NEXT: v_mul_hi_u32 v10, s7, v4
; CGP-NEXT: v_mul_lo_u32 v9, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_mov_b32_e32 v9, s6
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v10, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8
@ -1796,6 +1796,7 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
@ -1887,21 +1888,20 @@ define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v6
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
; CHECK-NEXT: v_mov_b32_e32 v7, s7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5]
; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v8, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6
@ -2247,14 +2247,14 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
@ -2285,7 +2285,7 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
@ -2310,7 +2310,7 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
@ -2332,26 +2332,26 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
; CGP-NEXT: v_mul_hi_u32 v12, s7, v7
; CGP-NEXT: v_mul_lo_u32 v11, s7, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11
; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_mov_b32_e32 v11, s8
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v12, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc
; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10
@ -2460,26 +2460,26 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v8, s7, v5
; CGP-NEXT: v_mul_hi_u32 v10, s7, v4
; CGP-NEXT: v_mul_lo_u32 v9, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_mov_b32_e32 v9, s6
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v10, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8

112
llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
View File

@ -1053,6 +1053,7 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
@ -1140,25 +1141,24 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_mov_b32_e32 v5, s7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v4
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v7, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
@ -1500,14 +1500,14 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
@ -1538,7 +1538,7 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
@ -1563,7 +1563,7 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
@ -1585,26 +1585,26 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v8, s7, v8
; CGP-NEXT: v_mul_lo_u32 v10, s7, v7
; CGP-NEXT: v_mul_hi_u32 v7, s7, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_mov_b32_e32 v9, s8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v11, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
; CGP-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc
; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s7, v9
; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
@ -1711,26 +1711,26 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v5, s7, v5
; CGP-NEXT: v_mul_lo_u32 v8, s7, v4
; CGP-NEXT: v_mul_hi_u32 v4, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mov_b32_e32 v7, s6
; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v9, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; CGP-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v7
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
@ -1768,6 +1768,7 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
@ -1855,25 +1856,24 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_mov_b32_e32 v5, s7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v4
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v7, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
@ -2215,14 +2215,14 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
@ -2253,7 +2253,7 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
@ -2278,7 +2278,7 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
@ -2300,26 +2300,26 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v8, s7, v8
; CGP-NEXT: v_mul_lo_u32 v10, s7, v7
; CGP-NEXT: v_mul_hi_u32 v7, s7, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_mov_b32_e32 v9, s8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v11, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
; CGP-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc
; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s7, v9
; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
@ -2426,26 +2426,26 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_mul_lo_u32 v5, s7, v5
; CGP-NEXT: v_mul_lo_u32 v8, s7, v4
; CGP-NEXT: v_mul_hi_u32 v4, s7, v4
; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mov_b32_e32 v7, s6
; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CGP-NEXT: v_mov_b32_e32 v9, s4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; CGP-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v7
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8

1482
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
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1886
llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
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1026
llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
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