forked from OSchip/llvm-project
[ARM] Some saturation instructions not DSP-only
Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
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aaec9b6cfc
commit
849f737155
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@ -3850,7 +3850,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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// Try to convert two saturating conditional selects into a single SSAT
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SDValue SatValue;
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uint64_t SatConstant;
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if (Subtarget->hasDSP() &&
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if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
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isSaturatingConditional(Op, SatValue, SatConstant))
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return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
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DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
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@ -3651,7 +3651,7 @@ def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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def SSAT : AI<(outs GPRnopc:$Rd),
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(ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
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SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
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Requires<[HasDSP]>{
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Requires<[IsARM,HasV6]>{
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bits<4> Rd;
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bits<5> sat_imm;
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bits<4> Rn;
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@ -3668,7 +3668,7 @@ def SSAT : AI<(outs GPRnopc:$Rd),
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def SSAT16 : AI<(outs GPRnopc:$Rd),
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(ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
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NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
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Requires<[HasDSP]>{
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Requires<[IsARM,HasV6]>{
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bits<4> Rd;
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bits<4> sat_imm;
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bits<4> Rn;
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@ -3682,7 +3682,7 @@ def SSAT16 : AI<(outs GPRnopc:$Rd),
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def USAT : AI<(outs GPRnopc:$Rd),
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(ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
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SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
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Requires<[HasDSP]>{
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Requires<[IsARM,HasV6]> {
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bits<4> Rd;
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bits<5> sat_imm;
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bits<4> Rn;
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@ -3699,7 +3699,7 @@ def USAT : AI<(outs GPRnopc:$Rd),
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def USAT16 : AI<(outs GPRnopc:$Rd),
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(ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
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NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
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Requires<[HasDSP]>{
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Requires<[IsARM,HasV6]>{
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bits<4> Rd;
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bits<4> sat_imm;
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bits<4> Rn;
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@ -2242,7 +2242,7 @@ def t2SSAT: T2SatI<
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(outs rGPR:$Rd),
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(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
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NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
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Requires<[IsThumb2, HasDSP]> {
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Requires<[IsThumb2]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1100;
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let Inst{20} = 0;
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@ -2268,7 +2268,7 @@ def t2USAT: T2SatI<
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(outs rGPR:$Rd),
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(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
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NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
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Requires<[IsThumb2, HasDSP]> {
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Requires<[IsThumb2]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1110;
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let Inst{20} = 0;
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