forked from OSchip/llvm-project
X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr
This is a re-commit ofe2c7ee0743which was reverted ina2a58d91e8. This includes a fix to consistently check for EFLAGS being live-out. See phabricator review. Original Summary: This extends `optimizeCompareInstr` to re-use previous comparison results if the previous comparison was with an immediate that was 1 bigger or smaller. Example: CMP x, 13 ... CMP x, 12 ; can be removed if we change the SETg SETg ... ; x > 12 changed to `SETge` (x >= 13) removing CMP Motivation: This often happens because SelectionDAG canonicalization tends to add/subtract 1 often when optimizing for fallthrough blocks. Example for `x > C` the fallthrough optimization switches true/false blocks with `!(x > C)` --> `x <= C` and canonicalization turns this into `x < C + 1`. Differential Revision: https://reviews.llvm.org/D110867
This commit is contained in:
Matthias Braun
parent
870fc844d1
commit
847a680733
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@ -4014,8 +4014,8 @@ bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
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Register SrcReg, Register SrcReg2,
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int64_t ImmMask, int64_t ImmValue,
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const MachineInstr &OI,
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bool *IsSwapped) const {
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const MachineInstr &OI, bool *IsSwapped,
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int64_t *ImmDelta) const {
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switch (OI.getOpcode()) {
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case X86::CMP64rr:
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case X86::CMP32rr:
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@ -4066,10 +4066,21 @@ bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
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int64_t OIMask;
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int64_t OIValue;
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if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
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SrcReg == OISrcReg && ImmMask == OIMask && OIValue == ImmValue) {
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assert(SrcReg2 == X86::NoRegister && OISrcReg2 == X86::NoRegister &&
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"should not have 2nd register");
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return true;
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SrcReg == OISrcReg && ImmMask == OIMask) {
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if (OIValue == ImmValue) {
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*ImmDelta = 0;
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return true;
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} else if (static_cast<uint64_t>(ImmValue) ==
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static_cast<uint64_t>(OIValue) - 1) {
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*ImmDelta = -1;
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return true;
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} else if (static_cast<uint64_t>(ImmValue) ==
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static_cast<uint64_t>(OIValue) + 1) {
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*ImmDelta = 1;
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return true;
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} else {
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return false;
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}
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}
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}
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return FlagI.isIdenticalTo(OI);
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@ -4319,6 +4330,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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bool ShouldUpdateCC = false;
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bool IsSwapped = false;
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X86::CondCode NewCC = X86::COND_INVALID;
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int64_t ImmDelta = 0;
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// Search backward from CmpInstr for the next instruction defining EFLAGS.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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@ -4365,7 +4377,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// ... // EFLAGS not changed
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// cmp x, y // <-- can be removed
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if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
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Inst, &IsSwapped)) {
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Inst, &IsSwapped, &ImmDelta)) {
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Sub = &Inst;
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break;
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}
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@ -4399,7 +4411,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// It is safe to remove CmpInstr if EFLAGS is redefined or killed.
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// If we are done with the basic block, we need to check whether EFLAGS is
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// live-out.
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bool IsSafe = false;
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bool FlagsMayLiveOut = true;
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SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
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MachineBasicBlock::iterator AfterCmpInstr =
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std::next(MachineBasicBlock::iterator(CmpInstr));
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@ -4409,7 +4421,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// We should check the usage if this instruction uses and updates EFLAGS.
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if (!UseEFLAGS && ModifyEFLAGS) {
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// It is safe to remove CmpInstr if EFLAGS is updated again.
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IsSafe = true;
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FlagsMayLiveOut = false;
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break;
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}
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if (!UseEFLAGS && !ModifyEFLAGS)
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@ -4417,7 +4429,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// EFLAGS is used by this instruction.
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X86::CondCode OldCC = X86::COND_INVALID;
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if (MI || IsSwapped) {
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if (MI || IsSwapped || ImmDelta != 0) {
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// We decode the condition code from opcode.
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if (Instr.isBranch())
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OldCC = X86::getCondFromBranch(Instr);
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@ -4470,9 +4482,59 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// We swap the condition code and synthesize the new opcode.
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ReplacementCC = getSwappedCondition(OldCC);
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if (ReplacementCC == X86::COND_INVALID) return false;
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ShouldUpdateCC = true;
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} else if (ImmDelta != 0) {
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unsigned BitWidth = TRI->getRegSizeInBits(*MRI->getRegClass(SrcReg));
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// Shift amount for min/max constants to adjust for 8/16/32 instruction
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// sizes.
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switch (OldCC) {
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case X86::COND_L: // x <s (C + 1) --> x <=s C
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if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
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return false;
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ReplacementCC = X86::COND_LE;
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break;
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case X86::COND_B: // x <u (C + 1) --> x <=u C
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if (ImmDelta != 1 || CmpValue == 0)
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return false;
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ReplacementCC = X86::COND_BE;
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break;
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case X86::COND_GE: // x >=s (C + 1) --> x >s C
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if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
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return false;
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ReplacementCC = X86::COND_G;
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break;
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case X86::COND_AE: // x >=u (C + 1) --> x >u C
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if (ImmDelta != 1 || CmpValue == 0)
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return false;
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ReplacementCC = X86::COND_A;
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break;
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case X86::COND_G: // x >s (C - 1) --> x >=s C
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if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
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return false;
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ReplacementCC = X86::COND_GE;
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break;
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case X86::COND_A: // x >u (C - 1) --> x >=u C
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if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
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return false;
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ReplacementCC = X86::COND_AE;
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break;
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case X86::COND_LE: // x <=s (C - 1) --> x <s C
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if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
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return false;
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ReplacementCC = X86::COND_L;
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break;
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case X86::COND_BE: // x <=u (C - 1) --> x <u C
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if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
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return false;
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ReplacementCC = X86::COND_B;
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break;
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default:
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return false;
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}
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ShouldUpdateCC = true;
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}
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if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
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if (ShouldUpdateCC && ReplacementCC != OldCC) {
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// Push the MachineInstr to OpsToUpdate.
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// If it is safe to remove CmpInstr, the condition code of these
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// instructions will be modified.
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@ -4480,14 +4542,14 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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}
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if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
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// It is safe to remove CmpInstr if EFLAGS is updated again or killed.
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IsSafe = true;
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FlagsMayLiveOut = false;
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break;
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}
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}
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// If EFLAGS is not killed nor re-defined, we should check whether it is
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// live-out. If it is live-out, do not optimize.
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if ((MI || IsSwapped) && !IsSafe) {
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// If we have to update users but EFLAGS is live-out abort, since we cannot
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// easily find all of the users.
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if (ShouldUpdateCC && FlagsMayLiveOut) {
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for (MachineBasicBlock *Successor : CmpMBB.successors())
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if (Successor->isLiveIn(X86::EFLAGS))
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return false;
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@ -640,7 +640,8 @@ private:
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/// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
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bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
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Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
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const MachineInstr &OI, bool *IsSwapped) const;
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const MachineInstr &OI, bool *IsSwapped,
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int64_t *ImmDelta) const;
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};
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} // namespace llvm
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@ -379,3 +379,307 @@ body: |
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CMP64ri32 %0, 24, implicit-def $eflags
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$cl = SETCCr 3, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_0
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_0
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: CMP64ri8 [[COPY]], 1, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 14, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 6, implicit $eflags
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%0:gr64 = COPY $rsi
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; CMP+SETCC %0 == 1
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CMP64ri8 %0, 1, implicit-def $eflags
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$cl = SETCCr 4, implicit $eflags
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; CMP+SETCC %0 >= 2; CMP can be removed.
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CMP64ri8 %0, 2, implicit-def $eflags
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; %0 >=s 2 --> %0 >s 1
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$bl = SETCCr 13, implicit $eflags
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; %0 >=u 2 --> %0 >u 1
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$bl = SETCCr 3, implicit $eflags
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; %0 <s 2 --> %0 <=s 1
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$bl = SETCCr 12, implicit $eflags
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; %0 <u 2 --> %0 <=u 1
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$bl = SETCCr 2, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_1
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_1
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: CMP64ri8 [[COPY]], 42, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 5, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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%0:gr64 = COPY $rsi
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; CMP+SETCC %0 != 42
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CMP64ri8 %0, 42, implicit-def $eflags
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$cl = SETCCr 5, implicit $eflags
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; CMP+SETCC %0 >= 2; CMP can be removed.
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CMP64ri8 %0, 41, implicit-def $eflags
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; %0 >s 41 --> %0 >=s 42
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$bl = SETCCr 15, implicit $eflags
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; %0 >u 41 --> %0 >=u 42
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$bl = SETCCr 7, implicit $eflags
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; %0 <=s 41 --> %0 <s 42
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$bl = SETCCr 14, implicit $eflags
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; %0 <=u 41 --> %0 <u 42
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$bl = SETCCr 6, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_test_cmp
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_test_cmp
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; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $bl
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; CHECK-NEXT: TEST8rr [[COPY]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 14, implicit $eflags
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; CHECK-NEXT: $cl = SETCCr 7, implicit $eflags
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; CHECK-NEXT: $cl = SETCCr 12, implicit $eflags
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%0:gr8 = COPY $bl
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TEST8rr %0, %0, implicit-def $eflags
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; SET %0 <=s 0
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$cl = SETCCr 14, implicit $eflags
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; CMP should be removed (%0 >=u 1)
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CMP8ri %0, 1, implicit-def $eflags
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$cl = SETCCr 3, implicit $eflags
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; CMP should be removed (%0 <=s -1)
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CMP8ri %0, -1, implicit-def $eflags
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$cl = SETCCr 14, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_cmp_test
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_cmp_test
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: CMP64ri32 [[COPY]], 1, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 13, implicit $eflags
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $edi
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; CHECK-NEXT: CMP64ri32 [[COPY1]], -1, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 14, implicit $eflags
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%0:gr64 = COPY $rsi
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CMP64ri32 %0, 1, implicit-def $eflags
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; TEST should be removed
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TEST64rr %0, %0, implicit-def $eflags
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$cl = SETCCr 15, implicit $eflags
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%1:gr64 = COPY $edi
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CMP64ri32 %1, -1, implicit-def $eflags
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; TEST should be removed
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TEST64rr %1, %1, implicit-def $eflags
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$cl = SETCCr 12, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_noopt_0
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_0
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: CMP64ri8 [[COPY]], 42, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
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; CHECK-NEXT: CMP64ri8 [[COPY]], 41, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 4, implicit $eflags
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%0:gr64 = COPY $rsi
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; CMP+SETCC %0 <s 1
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CMP64ri8 %0, 42, implicit-def $eflags
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$cl = SETCCr 4, implicit $eflags
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; CMP should not be removed.
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CMP64ri8 %0, 41, implicit-def $eflags
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; %0 == 41
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$bl = SETCCr 4, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_noopt_1
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_1
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
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; CHECK-NEXT: CMP32ri [[COPY]], 2147483647, implicit-def $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], -2147483648, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], 4294967295, implicit-def $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], -2147483648, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], 2147483647, implicit-def $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], -2147483648, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], 4294967295, implicit-def $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], 0, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], 4294967295, implicit-def $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], 0, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
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%0:gr32 = COPY $esi
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; CMP+SETCC %0 == INT32_MAX
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CMP32ri %0, 2147483647, implicit-def $eflags
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; CMP should not be removed.
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CMP32ri %0, -2147483648, implicit-def $eflags
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; %0 <s INT32_MIN
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$bl = SETCCr 12, implicit $eflags
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CMP32ri %0, 4294967295, implicit-def $eflags
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; CMP should not be removed.
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CMP32ri %0, -2147483648, implicit-def $eflags
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$bl = SETCCr 12, implicit $eflags
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CMP32ri %0, 2147483647, implicit-def $eflags
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; CMP should not be removed.
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CMP32ri %0, -2147483648, implicit-def $eflags
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$bl = SETCCr 13, implicit $eflags
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CMP32ri %0, 4294967295, implicit-def $eflags
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; should not be removed
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CMP32ri %0, 0, implicit-def $eflags
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$bl = SETCCr 2, implicit $eflags
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CMP32ri %0, 4294967295, implicit-def $eflags
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; should not be removed
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CMP32ri %0, 0, implicit-def $eflags
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$bl = SETCCr 3, implicit $eflags
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...
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---
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name: opt_redundant_flags_adjusted_imm_noopt_2
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body: |
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bb.0:
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; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_2
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; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $cx
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; CHECK-NEXT: CMP16ri [[COPY]], -32768, implicit-def $eflags
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; CHECK-NEXT: CMP16ri [[COPY]], 32767, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
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; CHECK-NEXT: CMP16ri [[COPY]], 65535, implicit-def $eflags
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; CHECK-NEXT: CMP16ri [[COPY]], 32767, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
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; CHECK-NEXT: CMP16ri [[COPY]], -32768, implicit-def $eflags
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; CHECK-NEXT: CMP16ri [[COPY]], 32767, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 14, implicit $eflags
|
||||
; CHECK-NEXT: CMP16ri [[COPY]], 0, implicit-def $eflags
|
||||
; CHECK-NEXT: CMP16ri [[COPY]], 65535, implicit-def $eflags
|
||||
; CHECK-NEXT: $bl = SETCCr 4, implicit $eflags
|
||||
; CHECK-NEXT: CMP16ri [[COPY]], 0, implicit-def $eflags
|
||||
; CHECK-NEXT: CMP16ri [[COPY]], 65535, implicit-def $eflags
|
||||
; CHECK-NEXT: $bl = SETCCr 6, implicit $eflags
|
||||
%0:gr16 = COPY $cx
|
||||
; CMP+SETCC %0 == INT16_MIN
|
||||
CMP16ri %0, -32768, implicit-def $eflags
|
||||
; CMP should not be removed.
|
||||
CMP16ri %0, 32767, implicit-def $eflags
|
||||
; %0 >s INT16_MAX
|
||||
$bl = SETCCr 15, implicit $eflags
|
||||
|
||||
CMP16ri %0, 65535, implicit-def $eflags
|
||||
; CMP should not be removed.
|
||||
CMP16ri %0, 32767, implicit-def $eflags
|
||||
$bl = SETCCr 15, implicit $eflags
|
||||
|
||||
CMP16ri %0, -32768, implicit-def $eflags
|
||||
; CMP should not be removed.
|
||||
CMP16ri %0, 32767, implicit-def $eflags
|
||||
$bl = SETCCr 14, implicit $eflags
|
||||
|
||||
CMP16ri %0, 0, implicit-def $eflags
|
||||
; should not be removed
|
||||
CMP16ri %0, 65535, implicit-def $eflags
|
||||
$bl = SETCCr 4, implicit $eflags
|
||||
|
||||
CMP16ri %0, 0, implicit-def $eflags
|
||||
; should not be removed
|
||||
CMP16ri %0, 65535, implicit-def $eflags
|
||||
$bl = SETCCr 6, implicit $eflags
|
||||
...
|
||||
---
|
||||
name: opt_adjusted_imm_multiple_blocks
|
||||
body: |
|
||||
; CHECK-LABEL: name: opt_adjusted_imm_multiple_blocks
|
||||
; CHECK: bb.0:
|
||||
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eax
|
||||
; CHECK-NEXT: CMP32ri [[COPY]], 20, implicit-def $eflags
|
||||
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
|
||||
; CHECK-NEXT: JMP_1 %bb.3
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.1:
|
||||
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags
|
||||
; CHECK-NEXT: JMP_1 %bb.3
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: JMP_1 %bb.3
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: RETQ
|
||||
bb.0:
|
||||
%0:gr32 = COPY $eax
|
||||
CMP32ri %0, 20, implicit-def $eflags
|
||||
JCC_1 %bb.1, 4, implicit $eflags
|
||||
JMP_1 %bb.3
|
||||
|
||||
bb.1:
|
||||
; CMP can be removed when adjusting the JCC.
|
||||
CMP32ri %0, 21, implicit-def $eflags
|
||||
JCC_1 %bb.2, 13, implicit $eflags
|
||||
JMP_1 %bb.3
|
||||
|
||||
bb.2:
|
||||
JMP_1 %bb.3
|
||||
|
||||
bb.3:
|
||||
RETQ
|
||||
...
|
||||
---
|
||||
name: opt_adjusted_imm_multiple_blocks_noopt
|
||||
body: |
|
||||
; CHECK-LABEL: name: opt_adjusted_imm_multiple_blocks_noopt
|
||||
; CHECK: bb.0:
|
||||
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eax
|
||||
; CHECK-NEXT: CMP32ri [[COPY]], 20, implicit-def $eflags
|
||||
; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
|
||||
; CHECK-NEXT: JMP_1 %bb.3
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.1:
|
||||
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: CMP32ri [[COPY]], 21, implicit-def $eflags
|
||||
; CHECK-NEXT: JCC_1 %bb.2, 13, implicit $eflags
|
||||
; CHECK-NEXT: JMP_1 %bb.3
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $al = SETCCr 4, implicit $eflags
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: RETQ
|
||||
bb.0:
|
||||
%0:gr32 = COPY $eax
|
||||
CMP32ri %0, 20, implicit-def $eflags
|
||||
JCC_1 %bb.1, 4, implicit $eflags
|
||||
JMP_1 %bb.3
|
||||
|
||||
bb.1:
|
||||
; The following CMP should not be optimized because $eflags is live-out
|
||||
CMP32ri %0, 21, implicit-def $eflags
|
||||
JCC_1 %bb.2, 13, implicit $eflags
|
||||
JMP_1 %bb.3
|
||||
|
||||
bb.2:
|
||||
liveins: $eflags
|
||||
$al = SETCCr 4, implicit $eflags
|
||||
|
||||
bb.3:
|
||||
RETQ
|
||||
...
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -o - %s -mtriple=x86_64-- | FileCheck %s
|
||||
; Example of a decref operation with "immortal" objects.
|
||||
; void decref(long* refcount) {
|
||||
; long count = *refcount;
|
||||
; if (count == 1) { free_object() }
|
||||
; else if (count > 1) { *refcount = count - 1; }
|
||||
; else { /* immortal */ }
|
||||
; }
|
||||
; Resulting assembly should share flags from single CMP instruction for both
|
||||
; conditions!
|
||||
define void @decref(i32* %p) {
|
||||
; CHECK-LABEL: decref:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pushq %rax
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||||
; CHECK-NEXT: movl (%rdi), %eax
|
||||
; CHECK-NEXT: cmpl $1, %eax
|
||||
; CHECK-NEXT: jne .LBB0_2
|
||||
; CHECK-NEXT: # %bb.1: # %bb_free
|
||||
; CHECK-NEXT: callq free_object@PLT
|
||||
; CHECK-NEXT: .LBB0_4: # %end
|
||||
; CHECK-NEXT: popq %rax
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 8
|
||||
; CHECK-NEXT: retq
|
||||
; CHECK-NEXT: .LBB0_2: # %bb2
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||||
; CHECK-NEXT: jle .LBB0_4
|
||||
; CHECK-NEXT: # %bb.3: # %bb_dec
|
||||
; CHECK-NEXT: decl %eax
|
||||
; CHECK-NEXT: movl %eax, (%rdi)
|
||||
; CHECK-NEXT: popq %rax
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 8
|
||||
; CHECK-NEXT: retq
|
||||
%count = load i32, i32* %p, align 4
|
||||
%cmp0 = icmp eq i32 %count, 1
|
||||
br i1 %cmp0, label %bb_free, label %bb2
|
||||
|
||||
bb2:
|
||||
%cmp1 = icmp sgt i32 %count, 1
|
||||
br i1 %cmp1, label %bb_dec, label %end
|
||||
|
||||
bb_dec:
|
||||
%dec = add nsw i32 %count, -1
|
||||
store i32 %dec, i32* %p, align 4
|
||||
br label %end
|
||||
|
||||
bb_free:
|
||||
call void @free_object()
|
||||
br label %end
|
||||
|
||||
end:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @free_object()
|
||||
|
|
@ -117,9 +117,8 @@ define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
|
|||
; CHECK-NEXT: cmpq $1, %rdx
|
||||
; CHECK-NEXT: jg .LBB3_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.end
|
||||
; CHECK-NEXT: testq %rdx, %rdx
|
||||
; CHECK-NEXT: movl $1, %ecx
|
||||
; CHECK-NEXT: cmovleq %rcx, %rax
|
||||
; CHECK-NEXT: cmovlq %rcx, %rax
|
||||
; CHECK-NEXT: imulq %rdi, %rax
|
||||
; CHECK-NEXT: .LBB3_2: # %return
|
||||
; CHECK-NEXT: retq
|
||||
|
|
@ -256,9 +255,8 @@ define i64 @ll_a_1(i64 %a, i64 %b) {
|
|||
; CHECK-NEXT: cmpq $1, %rdi
|
||||
; CHECK-NEXT: jg .LBB8_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.end
|
||||
; CHECK-NEXT: testq %rdi, %rdi
|
||||
; CHECK-NEXT: movl $1, %ecx
|
||||
; CHECK-NEXT: cmovleq %rcx, %rax
|
||||
; CHECK-NEXT: cmovlq %rcx, %rax
|
||||
; CHECK-NEXT: imulq %rdi, %rax
|
||||
; CHECK-NEXT: .LBB8_2: # %return
|
||||
; CHECK-NEXT: retq
|
||||
|
|
@ -412,9 +410,8 @@ define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
|
|||
; CHECK-NEXT: cmpl $1, %eax
|
||||
; CHECK-NEXT: jg .LBB13_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.end
|
||||
; CHECK-NEXT: testl %eax, %eax
|
||||
; CHECK-NEXT: movl $1, %eax
|
||||
; CHECK-NEXT: cmovlel %eax, %ecx
|
||||
; CHECK-NEXT: cmovll %eax, %ecx
|
||||
; CHECK-NEXT: imull %edi, %ecx
|
||||
; CHECK-NEXT: .LBB13_2: # %return
|
||||
; CHECK-NEXT: movslq %ecx, %rax
|
||||
|
|
@ -563,9 +560,8 @@ define i64 @i_a_1(i32 signext %a, i32 signext %b) {
|
|||
; CHECK-NEXT: cmpl $1, %edi
|
||||
; CHECK-NEXT: jg .LBB18_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.end
|
||||
; CHECK-NEXT: testl %edi, %edi
|
||||
; CHECK-NEXT: movl $1, %eax
|
||||
; CHECK-NEXT: cmovlel %eax, %esi
|
||||
; CHECK-NEXT: cmovll %eax, %esi
|
||||
; CHECK-NEXT: imull %edi, %esi
|
||||
; CHECK-NEXT: .LBB18_2: # %return
|
||||
; CHECK-NEXT: movslq %esi, %rax
|
||||
|
|
|
|||
Loading…
Reference in New Issue