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[SVE] Remove calls to isScalable from AARCH64 

Reviewers: efriedma, sdesmalen, t.p.northover, mcrosier

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77758
This commit is contained in:
Christopher Tetreault 2020-04-23 13:00:59 -07:00
parent 479145a5c2
commit 84584b0d29
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -9728,7 +9728,7 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
return false;
// FIXME: Update this method to support scalable addressing modes.
if (Ty->isVectorTy() && cast<VectorType>(Ty)->isScalable())
if (isa<ScalableVectorType>(Ty))
return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale;
// check reg + imm case: